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401 条记录 (耗时 0.029 秒)

    A/D conversion circuit
    2.
    发明授权
    A/D conversion circuit 有权

    公开(公告)号：US09838028B1

    公开(公告)日：2017-12-05

    申请号：US15595106

    申请日：2017-05-15

    申请人： ROHM CO., LTD.

    发明人： Haruhisa Yamaguchi ,  Kinji Ito

    IPC分类号： H03M1/10 ,  H03M1/06 ,  H01L27/02 ,  H03M1/34 ,  H03M1/12 ,  H03M1/00 ,  H03M1/78

    CPC分类号： H03M1/1076 ,  H01L27/02 ,  H03M1/00 ,  H03M1/0602 ,  H03M1/0697 ,  H03M1/1038 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/34 ,  H03M1/785

    摘要： An A/D conversion circuit includes a reference voltage source to generate a calibration voltage, a multiplexer to receive an analog signal and the calibration voltage, and output the analog signal selected in a normal mode and the calibration voltage selected in a calibration mode or a self-diagnosis mode, an A/D converter to convert an output signal from the multiplexer into a digital signal, a non-volatile memory to hold the digital signal and calibration data, a digital calibration part to calibrate the digital signal in case of inputting the analog signal to the A/D converter in the normal mode based on the calibration data, and a self-diagnosis circuit to diagnose the A/D converter based on the digital signal in case of inputting the calibration voltage to the A/D converter in the self-diagnosis mode, and the digital signal stored in the non-volatile memory.

    DIGITAL-TO-ANALOG CONVERTER AND SOURCE DRIVER USING THE SAME
    5.
    发明申请
    DIGITAL-TO-ANALOG CONVERTER AND SOURCE DRIVER USING THE SAME 有权

    公开(公告)号：US20170272092A1

    公开(公告)日：2017-09-21

    申请号：US15464986

    申请日：2017-03-21

    申请人： INNOAXIS CO., LTD

    发明人： Hwi-Cheol KIM

    IPC分类号： H03M1/66 ,  G09G3/20 ,  H03M7/30

    CPC分类号： H03M1/66 ,  G09G3/2007 ,  G09G2310/027 ,  G09G2320/0276 ,  H03M1/00 ,  H03M1/747 ,  H03M1/76 ,  H03M1/785 ,  H03M7/30

    摘要： A digital-to-analog converter including a resistor string configured to provide a plurality of gradation voltages formed by receiving a top voltage at one end thereof and a bottom voltage at the other end; a plurality of pass transistors including a pass transistor having one end which is electrically connected to the resistor string and outputting any one among the plurality of gradation voltages; and a decoder configured to control the plurality of pass transistors. The plurality of the pass transistors are included in any one among a plurality of groups according to values of the gradation voltages, and the pass transistors included in the any one group are divided into a first group and a second group according to output gradation voltages, and pass transistors included in the first group and pass transistors included in the second group are different types of pass transistors.

    Switchable secondary playback path
    6.
    发明授权
    Switchable secondary playback path 有权

    公开(公告)号：US09680488B2

    公开(公告)日：2017-06-13

    申请号：US15050857

    申请日：2016-02-23

    申请人： Cirrus Logic, Inc.

    发明人： Tejasvi Das ,  John L. Melanson ,  John C. Tucker ,  Xiaofan Fei

    IPC分类号： H03M1/78 ,  H03M1/00 ,  H03M1/08 ,  H03M1/66 ,  H03M1/70 ,  H03M1/68 ,  H03M3/00

    CPC分类号： H03M1/002 ,  H03M1/0845 ,  H03M1/66 ,  H03M1/662 ,  H03M1/68 ,  H03M1/70 ,  H03M1/785 ,  H03M3/32 ,  H03M3/392 ,  H03M3/414 ,  H03M3/416 ,  H03M3/50

    摘要： In accordance with embodiments of the present disclosure, a processing system may include a plurality of processing paths including a first processing path and a second processing path, a digital-to-analog stage output, and a controller. The first processing path may include a first digital-to-analog converter for converting the digital input signal into a first intermediate analog signal, the first digital-to-analog converter configured to operate in a high-power state and a low-power state. The second processing path may include a second digital-to-analog converter for converting a digital input signal into a second intermediate analog signal. The digital-to-analog stage output may be configured to generate an analog signal comprising a sum of the first intermediate analog signal and the second intermediate analog signal. The controller may be configured to operate the first digital-to-analog converter in the lower-power state when a magnitude of the digital input signal is below a threshold magnitude.

    DIGITAL-ANALOGUE CONVERTER FOR MULTI-THRESHOLD COUNTERS WITH PARTITIONING OF THE BITS BETWEEN RESISTOR LADDER AND COMPARATOR
    8.
    发明申请
    DIGITAL-ANALOGUE CONVERTER FOR MULTI-THRESHOLD COUNTERS WITH PARTITIONING OF THE BITS BETWEEN RESISTOR LADDER AND COMPARATOR 审中-公开

    公开(公告)号：US20170090048A1

    公开(公告)日：2017-03-30

    申请号：US15263522

    申请日：2016-09-13

    申请人： Siemens Healthcare GmbH

    发明人： Martin GROEPL ,  Edgar GOEDERER ,  Thomas SUTTORP

    IPC分类号： G01T1/24 ,  H03M1/66 ,  H03M1/78

    CPC分类号： G01T1/247 ,  H03M1/662 ,  H03M1/68 ,  H03M1/785 ,  H03M1/808

    摘要： An X-ray detector includes an N-channel digital-analogue converter controllable with K+L bits. In an embodiment, the digital-analogue converter includes a first voltage source to provide a plurality of first voltage values at tapping points; and a switch unit with N switch matrices, 2K inputs of the switch matrices being electrically conductively connected to 2K tapping points of the first voltage source. The digital-analogue converter also includes a second voltage source including N subunits. The X-ray detector further includes a discriminator unit including N comparators, at least one input of the comparators being electrically conductively connected to the associated output of the switch matrix and/or to the associated output of the subunit, so that the associated first voltage value and the associated second voltage value are associable with each comparator. A signal of an output of a pre-amplifier, and the associated first and second voltage values are comparable in the comparator.

    CALIBRATION TECHNIQUE FOR CURRENT STEERING DAC
    9.
    发明申请
    CALIBRATION TECHNIQUE FOR CURRENT STEERING DAC 有权
    电流转向DAC的校准技术

    公开(公告)号：US20170041014A1

    公开(公告)日：2017-02-09

    申请号：US15048027

    申请日：2016-02-19

    申请人： Texas Instruments Incorporated

    发明人： Neeraj SHRIVASTAVA ,  Supreet JOSHI ,  Himanshu VARSHNEY ,  Jafar Sadique KAVILADATH ,  Visvesvaraya PENTAKOTA ,  Shagun DUSAD

    IPC分类号： H03M1/10 ,  H03M1/74 ,  H03M1/78

    CPC分类号： H03M1/1009 ,  H03M1/1019 ,  H03M1/1057 ,  H03M1/66 ,  H03M1/742 ,  H03M1/745 ,  H03M1/785

    摘要： The disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.

    摘要翻译： 本公开提供了包括多个DAC元件的电流转向数模转换器（DAC）。 多个DAC元件中的至少一个DAC元件耦合到校准电路。 校准电路包括通过第一估计开关耦合到DAC元件的主节点的固定电流源。 数字码发生器耦合到主节点，并且产生对应于在主节点处产生的主电压的第一数字码。 数字代码生成器产生第二数字代码。 校正DAC耦合到数字代码发生器并且基于第二数字代码产生偏置电压。 偏置电压被提供给DAC元件，使得流过多个DAC元件中的每个DAC元件的电流相等。

    Multiple stage digital to analog converter
    10.
    发明授权
    Multiple stage digital to analog converter 有权
    多级数模转换器

    公开(公告)号：US09444487B1

    公开(公告)日：2016-09-13

    申请号：US14838097

    申请日：2015-08-27

    申请人： ANALOG DEVICES GLOBAL

    发明人： Dennis A. Dempsey

    IPC分类号： H03M1/38 ,  H03M1/78 ,  H03M1/68

    CPC分类号： H03M1/785 ,  H03M1/682 ,  H03M1/765

    摘要： In an example, there is disclosed a multi-stage Digital to Analog Convertor, including: a first stage having a first set of circuit components, a second stage having a second set of circuit components and a third stage having a third set of circuit components, the third stage providing a load within first and second individual switchable impedance paths; wherein the DAC is operable in each of a first mode, a second mode and a third mode of operation, wherein in a first mode the first stage is switchably coupled to the second stage independently of the third stage; in a second mode, the load is coupled and presented to a first part of the second stage of circuit components and in a third mode the load is coupled and presented to a second, different, part of the second stage of circuit components. A corresponding system and method is also disclosed.

    摘要翻译： 在一个示例中，公开了一种多级数模转换器，包括：第一级具有第一组电路部件，第二级具有第二组电路部件，第三级具有第三组电路部件 第三级在第一和第二可转换的阻抗路径内提供负载; 其中所述DAC可在第一模式，第二模式和第三操作模式中的每一个中操作，其中在第一模式中，所述第一级可独立于所述第三级可切换地耦合到所述第二级; 在第二模式中，负载被耦合并呈现给电路部件的第二级的第一部分，并且在第三模式中，负载耦合并呈现给第二级电路部件的第二，不同部分。 还公开了相应的系统和方法。