公开(公告)号：US20240074194A1

公开(公告)日：2024-02-29

申请号：US18237661

申请日：2023-08-24

Applicant: Micron Technology, Inc.

Inventor： Shruthi Kumara Vadivel ,  Harsh Narendrakumar Jain ,  Richard T. Housley ,  Zhenxing Han ,  Scott L. Light ,  Qinglin Zeng ,  Hsiao-Kuan Yuan ,  Jordan Chess ,  Xiaosong Zhang

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another; a first staircase structure formed in the tiers; a second staircase structure formed in the tiers adjacent the first staircase structure, respective portions of conductive materials in the tiers forming a part of the first and second staircase structure and a part of respective control gates associated with memory cells; a first trench structure formed in the tiers adjacent the first staircase structure and the second staircase structure, the first trench structure including length in a direction from the first staircase structure to the second staircase structure; and a second trench structure formed in the tiers adjacent the first trench structure, the second trench structure including a length in the direction from the first staircase structure to the second staircase structure.