公开(公告)号：US12237259B2

公开(公告)日：2025-02-25

申请号：US17443531

申请日：2021-07-27

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Harsh Narendrakumar Jain ,  Naveen Kaushik ,  Adam L. Olson ,  Richard J. Hill ,  Lars P. Heineck

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H10B41/35 ,  H10B43/35

Abstract: An electronic device comprising multilevel bitlines comprising first bitlines and second bitlines. The first bitlines and the second bitlines are positioned at different levels. Pillar contacts are electrically connected to the first bitlines and to the second bitlines. Level 1 contacts are electrically connected to the first bitlines and level 2 contacts are electrically connected to the second bitlines. A liner is between the first bitlines and the level 2 contacts. Each bitline of the first bitlines is electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Methods of forming an electronic device and related systems are also disclosed.

公开(公告)号：US20230395510A1

公开(公告)日：2023-12-07

申请号：US17812141

申请日：2022-07-12

Applicant: Micron Technology, Inc.

Inventor： Mithun Kumar Ramasahayam ,  Jordan D. Greenlee ,  Harsh Narendrakumar Jain ,  Jiewei Chen ,  Indra V. Chary

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53242 ,  H01L23/53257 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76888

Abstract: Microelectronic devices include a stack with a vertically alternating sequence of insulative and conductive structures arranged in tiers. A staircased stadium within the stack comprises steps at different tier elevations of a group of the tiers. Treads of the steps are each provided by an upper surface area of one of the conductive structures within the group of the tiers and by an upper surface area of a metal oxide region extending through the one of the conductive structures. A pair of conductive contact structures extends to one of the steps. A first conductive contact structure of the pair terminates at the tread of the step, within the area of the conductive structure. A second conductive contact structure of the pair extends through the tread of the step, within the upper surface area of the metal oxide region. Related fabrication methods and electronic systems are also disclosed.

公开(公告)号：US11785775B2

公开(公告)日：2023-10-10

申请号：US17153740

申请日：2021-01-20

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Shuangqiang Luo ,  Harsh Narendrakumar Jain ,  Nancy M. Lomeli ,  Christopher J. Larsen

IPC: H10B43/35 ,  H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/35 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/562 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a stack structure having an alternating sequence of conductive structures and insulative structures, an upper stadium structure, a lower stadium structure, and a crest region defined between a first stair step structure of the upper stadium structure and a second stair step structure of the lower stadium structure. The stack structure further includes pillar structures extending through the stack structure and dielectric structures interposed between neighboring pillar structures within the upper stadium structure. The method further includes forming a trench in the crest region of the stack structure between two dielectric structures of the dielectric structures on opposing sides of another dielectric structure and filling the trench with a dielectric material. The trench partially overlaps with the dielectric structures.

公开(公告)号：US20230033803A1

公开(公告)日：2023-02-02

申请号：US17443531

申请日：2021-07-27

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Harsh Narendrakumar Jain ,  Naveen Kaushik ,  Adam L. Olson ,  Richard J. Hill ,  Lars P. Heineck

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: An electronic device comprising multilevel bitlines comprising first bitlines and second bitlines. The first bitlines and the second bitlines are positioned at different levels. Pillar contacts are electrically connected to the first bitlines and to the second bitlines. Level 1 contacts are electrically connected to the first bitlines and level 2 contacts are electrically connected to the second bitlines. A liner is between the first bitlines and the level 2 contacts. Each bitline of the first bitlines is electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Methods of forming an electronic device and related systems are also disclosed.

公开(公告)号：US20230032177A1

公开(公告)日：2023-02-02

申请号：US17443521

申请日：2021-07-27

Applicant: Micron Technology, Inc.

Inventor： Harsh Narendrakumar Jain ,  Adam L. Olson ,  Yoshiaki Fukuzumi ,  Naveen Kaushik ,  Richard J. Hill ,  Lars P. Heineck

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  H01L23/00

Abstract: An electronic device comprising multilevel bitlines, pillar contacts, level 1 contacts, and level 2 contacts. The multilevel bitlines comprise first bitlines and second bitlines, with the first bitlines and second bitlines positioned at different levels. The pillar contacts are electrically connected to the first bitlines and to the second bitlines, the level 1 contacts are electrically connected to the first bitlines, and the level 2 contacts are electrically connected to the second bitlines. Each bitline of the first bitlines is electrically connected to a single pillar contact adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US20220068827A1

公开(公告)日：2022-03-03

申请号：US17006600

申请日：2020-08-28

Applicant: Micron Technology, Inc.

Inventor： Harsh Narendrakumar Jain

IPC: H01L23/532 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A microelectronic device comprises a first deck structure comprising alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, a second deck structure vertically overlying the first deck structure and comprising additional tiers of the conductive structures and insulative structures, a staircase structure within the first deck structure and having steps comprising edges of the tiers, a dielectric material covering the steps of the staircase structure and extending through the first deck structure, and a liner material interposed between the steps of the staircase structure and terminating at an interdeck region between the first deck structure and the second deck structure. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US11183456B2

公开(公告)日：2021-11-23

申请号：US16743329

申请日：2020-01-15

Applicant: Micron Technology, Inc.

Inventor： Harsh Narendrakumar Jain ,  Shuangqiang Luo

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L23/48 ,  H01L23/528 ,  H01L21/311 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers having channel-material strings therein. Conductive vias are formed through insulating material that is directly above the channel-material strings. Individual of the conductive vias are directly electrically coupled to individual of the channel-material strings. After forming the conductive vias, horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Intervening material is formed in the trenches laterally-between and longitudinally-along the immediately-laterally-adjacent memory-block regions. Additional methods and structures independent of method are disclosed.

公开(公告)号：US20210217694A1

公开(公告)日：2021-07-15

申请号：US16743329

申请日：2020-01-15

Applicant: Micron Technology, Inc.

Inventor： Harsh Narendrakumar Jain ,  Shuangqiang Luo

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L21/762 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers having channel-material strings therein. Conductive vias are formed through insulating material that is directly above the channel-material strings. Individual of the conductive vias are directly electrically coupled to individual of the channel-material strings. After forming the conductive vias, horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Intervening material is formed in the trenches laterally-between and longitudinally-along the immediately-laterally-adjacent memory-block regions. Additional methods and structures independent of method are disclosed.

公开(公告)号：US10985179B2

公开(公告)日：2021-04-20

申请号：US16532019

申请日：2019-08-05

Applicant: Micron Technology, inc.

Inventor： Yi Hu ,  Merri L. Carlson ,  Anilkumar Chandolu ,  Indra V. Chary ,  David Daycock ,  Harsh Narendrakumar Jain ,  Matthew J. King ,  Jian Li ,  Brett D. Lowe ,  Prakash Rau Mokhna Rau ,  Lifang Xu

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/768 ,  H01L27/115 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11573 ,  H01L21/3213

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

公开(公告)号：US20250006655A1

公开(公告)日：2025-01-02

申请号：US18750247

申请日：2024-06-21

Applicant: Micron Technology, Inc.

Inventor： Shruthi Kumara Vadivel ,  Harsh Narendrakumar Jain ,  Lance David Williamson ,  Kaveri Jain ,  Adam Lewis Olson

IPC: H01L23/544 ,  H01L21/311

Abstract: Aligning pillars of a three-dimensional NAND memory assembly can include forming a first pillar and a corresponding first pillar alignment feature in at least a portion of a first substrate stack. The alignment method can include depositing a second substrate stack on the first substrate stack, covering the first pillar alignment feature and the first pillar, and depositing a first masking layer on at least a portion of the second substrate stack. Illumination light can be used to illuminate a portion of the first masking layer. A reflected portion of the illumination light can indicate a location of the first pillar alignment feature corresponding to the first pillar. Particular wavelengths of the illumination light can be blocked or filtered by the first masking layer.