METHODS AND SYSTEMS FOR SHARING INFORMATION BETWEEN PROCESSORS
    1.
    发明申请
    METHODS AND SYSTEMS FOR SHARING INFORMATION BETWEEN PROCESSORS 有权
    处理器之间共享信息的方法和系统

    公开(公告)号:US20160103779A1

    公开(公告)日:2016-04-14

    申请号:US14510859

    申请日:2014-10-09

    Applicant: NETAPP, INC.

    CPC classification number: G06F13/4031 G06F13/4282

    Abstract: Methods and systems for sharing access to a computer resource accessible by a bus between two controllers are provided. For example, a machine implemented method of sharing access to computer resources includes requesting access to a bus from a processor of a first controller to access a device shared with a processor of a second controller; waiting for a positive response from the second controller; when the positive response is received, accessing the bus for less than a first timeout period; resetting a timer before the timer reaches the first timeout period to extend access to the bus, when access is not complete and a total access time is less than a second timeout period; and releasing the bus when access is complete or the second timeout period has been reached.

    Abstract translation: 提供了用于共享对由两个控制器之间的总线可访问的计算机资源的访问的方法和系统。 例如,共享对计算机资源的访问的机器实现方法包括请求从第一控制器的处理器访问总线以访问与第二控制器的处理器共享的设备; 等待第二控制器的积极响应; 当接收到正响应时,访问总线少于第一超时时间段; 在定时器到达第一超时周期之前重置定时器,以便在访问不完整并且总访问时间小于第二超时时段时扩展对总线的访问; 并在访问完成或达到第二个超时时间后释放总线。

    Methods and systems for sharing information between processors

    公开(公告)号:US10002098B2

    公开(公告)日:2018-06-19

    申请号:US14510859

    申请日:2014-10-09

    Applicant: NETAPP, INC.

    CPC classification number: G06F13/4031 G06F13/4282

    Abstract: Methods and systems for sharing access to a computer resource accessible by a bus between two controllers are provided. For example, a machine implemented method of sharing access to computer resources includes requesting access to a bus from a processor of a first controller to access a device shared with a processor of a second controller; waiting for a positive response from the second controller; when the positive response is received, accessing the bus for less than a first timeout period; resetting a timer before the timer reaches the first timeout period to extend access to the bus, when access is not complete and a total access time is less than a second timeout period; and releasing the bus when access is complete or the second timeout period has been reached.

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