公开(公告)号：US20140062556A1

公开(公告)日：2014-03-06

申请号：US13670466

申请日：2012-11-07

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Yi-Kuang Chen

IPC: H03L7/24 ,  H03L7/00

CPC classification number: H03K23/40 ,  H03K23/68

Abstract: A multiphase clock divider includes: a reference clock generator for generating a plurality of reference clocks; and at least one output clock generator including a first multiplexer for selecting to output a selected reference clock, a second multiplexer for selecting to output a first selected input clock, a third multiplexer for selecting to output a second selected input clock, a first flip-flop for outputting a first sampling clock according to the selected reference clock and the first selected input clock, a second flip-flop for outputting a second sampling clock according to the first sampling clock and the second selected input clock, and a fourth multiplexer for selecting to output the first sampling clock or the second sampling clock to generate an output clock.

Abstract translation: 多相时钟分频器包括：用于产生多个参考时钟的参考时钟发生器; 以及至少一个输出时钟发生器，包括用于选择输出所选择的参考时钟的第一多路复用器，用于选择输出第一选择的输入时钟的第二多路复用器，用于选择输出第二选择的输入时钟的第三多路复用器， 触发器，用于根据所选择的参考时钟和第一选择的输入时钟输出第一采样时钟;第二触发器，用于根据第一采样时钟和第二选择的输入时钟输出第二采样时钟;以及第四多路复用器，用于选择 以输出第一采样时钟或第二采样时钟以产生输出时钟。

公开(公告)号：US08736318B2

公开(公告)日：2014-05-27

申请号：US13670466

申请日：2012-11-07

Applicant: NOVATEK Microelectronics Corp.

Inventor： Yi-Kuang Chen

IPC: H03K23/00

CPC classification number: H03K23/40 ,  H03K23/68

Abstract: A multiphase clock divider includes: a reference clock generator for generating a plurality of reference clocks; and at least one output clock generator including a first multiplexer for selecting to output a selected reference clock, a second multiplexer for selecting to output a first selected input clock, a third multiplexer for selecting to output a second selected input clock, a first flip-flop for outputting a first sampling clock according to the selected reference clock and the first selected input clock, a second flip-flop for outputting a second sampling clock according to the first sampling clock and the second selected input clock, and a fourth multiplexer for selecting to output the first sampling clock or the second sampling clock to generate an output clock.

Abstract translation: 多相时钟分频器包括：用于产生多个参考时钟的参考时钟发生器; 以及至少一个输出时钟发生器，包括用于选择输出所选择的参考时钟的第一多路复用器，用于选择输出第一选择的输入时钟的第二多路复用器，用于选择输出第二选择的输入时钟的第三多路复用器， 触发器，用于根据所选择的参考时钟和第一选择的输入时钟输出第一采样时钟;第二触发器，用于根据第一采样时钟和第二选择的输入时钟输出第二采样时钟;以及第四多路复用器，用于选择 以输出第一采样时钟或第二采样时钟以产生输出时钟。