公开(公告)号：US11800046B2

公开(公告)日：2023-10-24

申请号：US16807802

申请日：2020-03-03

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Jhih-Siou Cheng ,  Yi-Chuan Liu ,  Hung-Cheng Hsiao ,  Ying-Wen Chou

IPC: H04N5/268 ,  H04N5/38 ,  H04N5/44 ,  G06F13/40

CPC classification number: H04N5/268 ,  G06F13/4086 ,  H04N5/38 ,  H04N5/44

Abstract: A video transmission system is disclosed. The video transmission system comprises a multi-drop bus, a first source driving chip, a second source driving chip and a timing controller. The first source driving chip comprises a first source driving circuit and a first terminal circuit. The first terminal circuit is coupled to the multi-drop bus and the first source driving circuit for providing a first terminal resistor. The second source driving chip comprises a second source driving circuit and a second terminal circuit. The second terminal circuit is coupled to the multi-drop bus and the second source driving circuit for providing a second terminal resistor. The timing controller is coupled to the first source driving chip and the second source driving chip via the multi-drop bus.

公开(公告)号：US09800800B2

公开(公告)日：2017-10-24

申请号：US14328078

申请日：2014-07-10

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Jhih-Siou Cheng ,  Yi-Chuan Liu ,  Hung-Cheng Hsiao ,  Ying-Wen Chou

IPC: H04N5/38 ,  H04N5/44 ,  H04N5/268 ,  G06F13/40

CPC classification number: H04N5/268 ,  G06F13/4086 ,  H04N5/38 ,  H04N5/44

Abstract: A video transmission system is disclosed. The video transmission system comprises a multi-drop bus, a first source driving chip, a second source driving chip and a timing controller. The first source driving chip comprises a first source driving circuit and a first terminal circuit. The first terminal circuit is coupled to the multi-drop bus and the first source driving circuit for providing a first terminal resistor. The second source driving chip comprises a second source driving circuit and a second terminal circuit. The second terminal circuit is coupled to the multi-drop bus and the second source driving circuit for providing a second terminal resistor. The timing controller is coupled to the first source driving chip and the second source driving chip via the multi-drop bus.