Abstract:
A display driver device including a driver circuit and a control circuit is provided. The driver circuit is configured to drive a display panel to display an animated image for a display period under an always on display mode according to display information of the animated image stored in a storage circuit. The display period includes a writing period and a non-writing period after the writing period. The control circuit is configured to write the display information of the animated image received from an external device into the storage circuit during the writing period of the display period. The control circuit is configured to stop receiving the display information from the external device and writing any display information into the storage circuit during the non-writing period of the display period. A display device including the display driver device and an operating method for the display driver device are also provided.
Abstract:
A display driver device including a driver circuit and a control circuit is provided. The driver circuit is configured to drive a display panel to display an animated image for a display period under an always on display mode according to display information of the animated image stored in a storage circuit. The display period includes a writing period and a non-writing period after the writing period. The control circuit is configured to write the display information of the animated image received from an external device into the storage circuit during the writing period of the display period. The control circuit is configured to stop receiving the display information from the external device and writing any display information into the storage circuit during the non-writing period of the display period. A display device including the display driver device and an operating method for the display driver device are also provided.
Abstract:
A display driving circuit, a calibration module, and an associated calibration method are provided. The display driving circuit includes an internal clock circuit and the calibration module. The internal clock circuit generates an internal clock signal. The calibration module includes a counting circuit and a trimming circuit. The counting circuit counts pulses of a reference clock signal to generate a detected reference-clock count and counts pulses of the internal clock signal to generate a detected internal-clock count. The trimming circuit generates a calibration signal to adjust frequency of the internal clock signal when a predefined condition is satisfied. The predefined condition is related to comparison between a first preset count and one of the detected reference-clock count and the detected internal-clock count.
Abstract:
A method of dynamic bias control of a source driver bases on data wing level for power-saving. In order to cover the operating conditions of various loads under normal operations, the output buffer circuit operation is biased. The method utilizes the display gray scale difference between a previous data line and an immediately subsequent data line to determine the bias current to be used for the output buffer. When the difference between the current data line display gray scale and the previous data line display gray scale is not large, the bias current of the output buffer can be reduced. When the difference between the current data line display gray scale and the previous data line display gray scale is large, the bias current of the output buffer is increased and the current of the output buffer is adjusted according to different load conditions to save power.
Abstract:
A driving device and an operation method thereof are provided. The driver device includes a source driver circuit, an output switching circuit, and an equalization control circuit. Two input ends of the output switching circuit are coupled to two output ends of the source driver circuit. Two output ends of the output switching circuit are coupled to two data lines of an LED display panel. The equalization control circuit checks whether sub-pixel data of the two data lines meets a predetermined condition. A plurality of sub-pixels located on a current display line of the LED display panel are reset in a reset period. In a data scanning period after the reset period, the equalization control circuit determines whether to control the output switching circuit to perform an equalization operation on the two data lines according to the checking result.
Abstract:
A method of controlling a source driver includes the steps of: detecting a line of image data to be outputted by a plurality of channels of the source driver, to generate a detection result; generating a plurality of control signals according to the detection result, each of the plurality of control signals corresponding to a channel among the plurality of channels; and enabling or disabling an operational amplifier in each of the plurality of channels via one of the plurality of control signals corresponding to the channel.
Abstract:
A data transmission system includes a transmission device having a first control module for generating a first control signal. A first transformation module is coupled to the first control module for transforming an original data into a transmission data according to the original data and the first control signal. A multiplexer is utilized for transmitting the transmission data according to the first control signal. A reception device includes a second control module for generating a second control signal, a reception module coupled to the second control module for receiving the transmission data, and a second transformation module for transforming the transmission data into the original data according to the second control signal, so as to transmit the original data to a display device. Thus, a transmission size of the transmission data is smaller than a transmission size of the original data.
Abstract:
A method of processing an image data for an image processing device includes a plurality of steps. The steps include receiving the image data; storing the image data in a frame buffer of the image processing device; performing a signal processing procedure on the image data obtained from the frame buffer, to generate a final display data; restoring the final display data in the frame buffer; and entering a power saving mode after the final display data is restored in the frame buffer. In the power saving mode, the image processing device performs the following steps: turning off the signal processing circuit; and outputting the final display data restored in the frame buffer, to display the final display data.
Abstract:
In the disclosure, a display driver integrated circuit (DDIC) configured to drive a display panel and an electronic apparatus having the DDIC would generate display data to constantly update information displayed on the display panel even when a processor is in a power save mode. The DDIC includes a first input terminal, a memory device, an information rendering unit, an information overlay unit, and a source driver. The first input terminal receives a subscribed signal. The memory device stores a background image. The information rendering unit is coupled to the first input terminal of the DDIC to receive the subscribed signal and renders subscribed information according to the subscribed signal. The information overlay unit receives the subscribed information from the information overlay unit and the background image from the memory device, and accordingly, the display data is generated without obtaining frame data from an external processor.
Abstract:
A semiconductor apparatus is provided. The semiconductor apparatus includes: a first circuit, including a first semiconductor substrate, a first group of circuit components formed on the first semiconductor substrate, and a first group of metal layers, wherein, the first group of circuit components are distributed to at least one circuit block, and traces for each circuit block are formed in at least some of the first group of metal layers; a second circuit, including a second semiconductor substrate, a second group of circuit components formed on the second semiconductor substrate, and a second group of metal layers, wherein, the second group of circuit components are distributed to at least one circuit block, and traces for each circuit block are formed in at least some of the second group of metal layers, and the first circuit and the second circuit being face-to-face stacked and bonded.