公开(公告)号：US20240056086A1

公开(公告)日：2024-02-15

申请号：US18496908

申请日：2023-10-29

Applicant: NOVATEK Microelectronics Corp.

Inventor： Chin-Tung CHAN ,  Yan-Ting WANG ,  Ren-Hong LUO ,  Chih-Wen CHEN ,  Hao-Che HSU ,  Li-Wei LIN

IPC: H03L7/099 ,  H03L7/23 ,  H03L7/085

CPC classification number: H03L7/099 ,  H03L7/23 ,  H03L7/085

Abstract: A frequency locked loop circuit, comprising an operational circuit, a first impedance circuit, a second impedance circuit, a switching circuit and a frequency generation circuit. The operational circuit is configured to output an operational signal according to a voltage difference between a positive terminal and a negative terminal. The switching circuit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and periodically conduct the positive terminal to the other one of the first impedance node and the second impedance node. The frequency generation circuit is configured to periodically sample the operational signal to generate a sample signal to generate a clock signal. An operational frequency of the operational signal is an integer multiple of a sampling frequency of the frequency generation circuit.

公开(公告)号：US20240106443A1

公开(公告)日：2024-03-28

申请号：US18534702

申请日：2023-12-10

Applicant: NOVATEK Microelectronics Corp.

Inventor： Chin-Tung CHAN

IPC: H03L7/099 ,  H03L7/085 ,  H03L7/23

CPC classification number: H03L7/099 ,  H03L7/085 ,  H03L7/23

Abstract: A switching method, including: electrically coupling a switching circuit to a first impedance circuit, a second impedance circuit, a positive terminal of a frequency generation circuit and a negative terminal of the frequency generation circuit; adjusting an impedance value of the second impedance circuit according to a first clock signal and a second clock signal outputted by the frequency generation circuit; periodically conducting the negative terminal to one of the first impedance circuit and the second impedance circuit by a first switching unit of the switching circuit; and periodically conducting the positive terminal to the other one of the first impedance circuit and the second impedance circuit by a second switching unit of the switching circuit.

公开(公告)号：US20210203330A1

公开(公告)日：2021-07-01

申请号：US16727882

申请日：2019-12-26

Applicant: NOVATEK Microelectronics Corp.

Inventor： Chin-Tung CHAN

IPC: H03L7/099 ,  H03L7/085 ,  H03L7/23

Abstract: A frequency locked loop circuit, including a frequency generation circuit, a first impedance circuit, a second impedance circuit and a switching circuit. The frequency generation circuit includes a positive terminal and a negative terminal. The frequency generation circuit outputs an output clock signal according to a voltage difference between the positive terminal and the negative terminal. The first impedance circuit and the second impedance circuit are electrically coupled to a first impedance node and a second impedance node, respectively. The second impedance circuit adjusts an impedance value of the second impedance circuit according to the output clock signal. The switching circuit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and periodically conduct the positive terminal to the other one of the first impedance node and the second impedance node.