公开(公告)号：US20170337886A1

公开(公告)日：2017-11-23

申请号：US15159777

申请日：2016-05-19

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Ren-Hong LUO ,  Shih-Chun LIN ,  Yung-Cheng LIN ,  Mu-Jung CHEN

IPC: G09G3/36 ,  H02M1/08 ,  H02M3/158

CPC classification number: G09G3/36 ,  G09G3/3611 ,  G09G2330/021 ,  G09G2370/08 ,  H02M1/088 ,  H02M2001/0045

Abstract: A voltage regulator and method applied thereto are provided. The voltage regulator generates a regulated voltage in response to a reference voltage and a control code. The voltage regulator includes a voltage divider circuit, an amplifier circuit, and a power MOS array. The voltage divider circuit is configured to divide the regulated voltage to generate a feedback voltage. The amplifier circuit is configured to amplify a voltage difference between the reference voltage and the feedback voltage to generate a bias voltage. The power MOS array includes multiple transistors. Each transistor has a first terminal coupled to a power rail, a second terminal coupled to the regulated voltage, and a control terminal selectively coupled to either the power rail or the bias voltage in response to the control code.

公开(公告)号：US20240056086A1

公开(公告)日：2024-02-15

申请号：US18496908

申请日：2023-10-29

Applicant: NOVATEK Microelectronics Corp.

Inventor： Chin-Tung CHAN ,  Yan-Ting WANG ,  Ren-Hong LUO ,  Chih-Wen CHEN ,  Hao-Che HSU ,  Li-Wei LIN

IPC: H03L7/099 ,  H03L7/23 ,  H03L7/085

CPC classification number: H03L7/099 ,  H03L7/23 ,  H03L7/085

Abstract: A frequency locked loop circuit, comprising an operational circuit, a first impedance circuit, a second impedance circuit, a switching circuit and a frequency generation circuit. The operational circuit is configured to output an operational signal according to a voltage difference between a positive terminal and a negative terminal. The switching circuit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and periodically conduct the positive terminal to the other one of the first impedance node and the second impedance node. The frequency generation circuit is configured to periodically sample the operational signal to generate a sample signal to generate a clock signal. An operational frequency of the operational signal is an integer multiple of a sampling frequency of the frequency generation circuit.