Wafer level chip scale semiconductor package

    公开(公告)号:US10109564B2

    公开(公告)日:2018-10-23

    申请号:US15431124

    申请日:2017-02-13

    Applicant: NXP B.V.

    Abstract: This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.

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