公开(公告)号：US20240393391A1

公开(公告)日：2024-11-28

申请号：US18360147

申请日：2023-07-27

Applicant: NXP B.V.

Inventor： Jorge Ernesto Perez Chamorro ,  Vasudev Srinivasan ,  Andreas Lentz ,  Jean-Michel Cioranesco

IPC: G01R31/317

Abstract: A fault detection system includes a state register, an error detection code (EDC) register, logic circuitry, an EDC generator, and an EDC checker. The state and EDC registers store first reference data and first checksum data, respectively. The logic circuitry executes a logic function based on the first reference data to iteratively generate second reference data that is different from the first reference data, and updates the first reference data of the state register with the second reference data of one iteration. The EDC generator iteratively generates second checksum data based on the iteratively generated second reference data and updates the first checksum data of the EDC register with the second checksum data of one iteration. The EDC checker detects a fault in the IC based on the updated first reference data and the updated first checksum data.

公开(公告)号：US20250005202A1

公开(公告)日：2025-01-02

申请号：US18754560

申请日：2024-07-16

Applicant: NXP B.V.

Inventor： Jorge Ernesto Perez Chamorro ,  Vasudev Srinivasan ,  Hugues Jean Marie de Perthuis

IPC: G06F21/64

Abstract: In accordance with a first aspect of the present disclosure, a storage device is provided, comprising: one or more special function registers; a preloading stage comprising a first preload register, wherein the preloading stage is configured to preload data in the first preload register before loading the preloaded data into the special function registers; wherein the preloading stage is further configured to perform a verification of the integrity of the preloaded data before loading said preloaded data into the special function registers. In accordance with a second aspect of the present disclosure, a corresponding method of operating a storage device is conceived.