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公开(公告)号：US11474130B2
公开(公告)日：2022-10-18
申请号：US16908338
申请日：2020-06-22
Applicant: NXP B.V.
Inventor： Andreas Lentz , Andreas Bernardus Maria Jansman
IPC: G01R19/165 , G06K19/073 , H03K5/1252
Abstract: An integrated circuit for hardware security comprises a voltage glitch detection processing system comprising an oscillator circuit that generates and outputs a local oscillator clock which is a function of a supply voltage; a counter clocked by the oscillator circuit to generate at least one count value; and a capture section that synchronizes the at least one count value into a system clock domain for detecting a voltage glitch in the supply voltage.
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公开(公告)号：US20240353888A1
公开(公告)日：2024-10-24
申请号：US18640347
申请日：2024-04-19
Applicant: NXP B.V.
Inventor： Andreas Lentz , David Paul Price
Abstract: The present disclosure relates to a clock signal monitoring unit comprising first, second and third flip-flops, first and second XOR gates and a delay element being functionally interconnected in a specific way. The proposed clock signal monitoring unit can detect both a rising edge glitch and a falling edge glitch. In this way there is provided an area saving device, which does not require any trimming efforts, which can save a lot of space and time. Furthermore, the clock signal monitoring unit can have low electric power consumption because it uses as few as four clocked flip-flops implemented via Register Transfer Logic having an already tuned delay element. This makes it useful for designs that use both edges of the clock for correct operation.
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公开(公告)号：US20220158820A1
公开(公告)日：2022-05-19
申请号：US17451198
申请日：2021-10-18
Applicant: NXP B.V.
Inventor： Jan-Peter Schat , Andreas Lentz , Fabrice Poulard
IPC: H04L9/06
Abstract: An apparatus configured to: receive a digital input signal; receive a processing-direction-signal that can have a forward-value or a backward-value; and provide a digital output signal. The apparatus comprising a processor configured to apply an involutional cryptographic function to the digital input signal by: for a first operation: apply a first step of the involutional cryptographic function to the digital input signal in order to implement a forward calculation to move to the next step in the sequence; and perform a plurality of further operations until the forward calculation of a last step is performed. Each further operation comprises: if the processing-direction-signal has a forward-value: then perform the forward calculation for the current step; or if the processing-direction-signal has a backward-value: then perform a backward calculation for the current step.
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公开(公告)号：US20240393391A1
公开(公告)日：2024-11-28
申请号：US18360147
申请日：2023-07-27
Applicant: NXP B.V.
Inventor： Jorge Ernesto Perez Chamorro , Vasudev Srinivasan , Andreas Lentz , Jean-Michel Cioranesco
IPC: G01R31/317
Abstract: A fault detection system includes a state register, an error detection code (EDC) register, logic circuitry, an EDC generator, and an EDC checker. The state and EDC registers store first reference data and first checksum data, respectively. The logic circuitry executes a logic function based on the first reference data to iteratively generate second reference data that is different from the first reference data, and updates the first reference data of the state register with the second reference data of one iteration. The EDC generator iteratively generates second checksum data based on the iteratively generated second reference data and updates the first checksum data of the EDC register with the second checksum data of one iteration. The EDC checker detects a fault in the IC based on the updated first reference data and the updated first checksum data.
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公开(公告)号：US11947672B2
公开(公告)日：2024-04-02
申请号：US17189329
申请日：2021-03-02
Applicant: NXP B.V.
Inventor： Andreas Bernardus Maria Jansman , Andreas Lentz
CPC classification number: G06F21/567 , G06F1/28 , G06F1/3296 , G06F21/81 , H03K3/0315 , H03K3/037 , H03K21/02 , G06F2221/034
Abstract: A voltage glitch detector includes a ring oscillator, a plurality of counters, a combined result circuit, and a result evaluation circuit. The ring oscillator includes a plurality of series-connected stages. An output of a last stage of the ring oscillator is coupled to an input of a first stage of the ring oscillator. Each counter of the plurality of counters has an input coupled to a node located between two stages of the plurality of series-connected stages. The combined result circuit is coupled to each of the plurality of counters. The combined result circuit combines the count values received from each counter of the plurality of counters to provide a combined result. The result evaluation circuit is coupled to compare the combined result with a reference value to determine when a voltage glitch is detected.
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Patent Agency Ranking
公开(公告)号：US11509461B2
公开(公告)日：2022-11-22
申请号：US17301780
申请日：2021-04-14
Applicant: NXP B.V.
Inventor： Jan-Peter Schat , Fabrice Poulard , Andreas Lentz
Abstract: A method for securing an integrated circuit chip includes obtaining a first value from a first storage area in the chip, obtaining a second value from a second storage area in the chip, generating a third value based on the first value and the second value, and converting a first opcode command obfuscated as a second opcode command into a non-obfuscated form of the first opcode command based on the third value. The first value corresponds to a physically unclonable function (PUF) of the chip. The second value is a key including information indicating a type of obfuscation performed to obfuscate the first opcode command as the second opcode command. The third value may be an inversion flag indicating a type of obfuscation performed to obfuscate the first opcode command as the second opcode command.
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公开(公告)号：US11355457B2
公开(公告)日：2022-06-07
申请号：US16445650
申请日：2019-06-19
Applicant: NXP B.V.
Inventor： Andreas Lentz , Stefan Heyse , Martin Heinrich Butkus , Oliver Alexander Schmidt
Abstract: A fully digital method and apparatus are provided for detecting glitches on a monitored line by providing a toggle signal to an initial delay circuit and a plurality of delay elements formed with standard logic cells so that logic values from the delay elements are captured in a corresponding plurality of clocked capture flops to provide a digitized representation of a delay value during a sampling period which is converted to a numerical measurement result which is evaluated against a reference value to generate an output error signal if a difference between the numerical measurement result and reference value exceeds a programmable margin, where the initial delay circuit is configured with a trim setting to impose an initial delay to compensate for process variations and where the reference value is adapted over a plurality of sampling periods to compensate for temperature effects on the numerical measurement result.
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公开(公告)号：US20210351922A1
公开(公告)日：2021-11-11
申请号：US17301780
申请日：2021-04-14
Applicant: NXP B.V.
Inventor： Jan-Peter Schat , Fabrice Poulard , Andreas Lentz
Abstract: A method for securing an integrated circuit chip includes obtaining a first value from a first storage area in the chip, obtaining a second value from a second storage area in the chip, generating a third value based on the first value and the second value, and converting a first opcode command obfuscated as a second opcode command into a non-obfuscated form of the first opcode command based on the third value. The first value corresponds to a physically unclonable function (PUF) of the chip. The second value is a key including information indicating a type of obfuscation performed to obfuscate the first opcode command as the second opcode command. The third value may be an inversion flag indicating a type of obfuscation performed to obfuscate the first opcode command as the second opcode command.
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9.发明授权公开(公告)号：US12047489B2
公开(公告)日：2024-07-23
申请号：US17451198
申请日：2021-10-18
Applicant: NXP B.V.
Inventor： Jan-Peter Schat , Andreas Lentz , Fabrice Poulard
CPC classification number: H04L9/0631 , H04L2209/16
Abstract: An apparatus configured to: receive a digital input signal; receive a processing-direction-signal that can have a forward-value or a backward-value; and provide a digital output signal. The apparatus comprising a processor configured to apply an involutional cryptographic function to the digital input signal by: for a first operation: apply a first step of the involutional cryptographic function to the digital input signal in order to implement a forward calculation to move to the next step in the sequence; and perform a plurality of further operations until the forward calculation of a last step is performed. Each further operation comprises: if the processing-direction-signal has a forward-value: then perform the forward calculation for the current step; or if the processing-direction-signal has a backward-value: then perform a backward calculation for the current step.
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公开(公告)号：US11689206B1
公开(公告)日：2023-06-27
申请号：US17686664
申请日：2022-03-04
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann , Andreas Lentz
IPC: H03L7/099
CPC classification number: H03L7/099 , H03L2207/50
Abstract: A method for clock frequency monitoring for a Phase-Locked Loop (PLL) based design includes determining a present operating point of an oscillator of the PLL based design, wherein the oscillator generates a present frequency in response to the present operating point. The present operating point of the oscillator is compared to a comparison range defined by a plurality of reference operating points, wherein the oscillator generates a nominal reference frequency in response to a nominal one of the plurality of reference operating points and the comparison range is further defined by a manufacturing process range, an operating voltage range and an operating temperature range. An action is performed in response to the present operating point being outside of the comparison range.
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