公开(公告)号：US20020130354A1

公开(公告)日：2002-09-19

申请号：US10095936

申请日：2002-03-13

Applicant: National Inst. of Advanced Ind. Science and Tech.

Inventor： Toshihiro Sekigawa ,  Kenichi Ishii ,  Eiichi Suzuki

IPC: H01L031/119 ,  H01L031/113 ,  H01L031/062 ,  H01L029/94 ,  H01L029/76

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818

Abstract: A double-gate field-effect transistor includes a substrate, an insulation film formed on the substrate, source, drain and channel regions formed on the insulation film from a semiconductor crystal layer, and two insulated gate electrodes electrically insulated from each other. The gate electrodes are formed opposite each other on the same principal surface as the channel region, with the channel region between the electrodes. The source, drain and channel regions are isolated from the surrounding part by a trench, forming an island. Gate insulation films are formed on the opposing side faces of the channel region exposed in the trench. The island region between the gate electrodes is given a width that is less than the length of the channel region to enhance the short channel effect suppressive property of structure.

Abstract translation: 双栅场效应晶体管包括基板，形成在基板上的绝缘膜，在半导体晶体层上形成在绝缘膜上的源极，漏极和沟道区域以及彼此电绝缘的两个绝缘栅电极。 栅电极在与沟道区相同的主表面上形成为彼此相对，电极之间具有沟道区。 源极，漏极和沟道区域通过沟槽与周围部分隔离，形成岛。 栅极绝缘膜形成在暴露在沟槽中的沟道区域的相对侧面上。 栅电极之间的岛区域的宽度小于通道区域的长度，以增强结构的短沟道效应抑制性能。