公开(公告)号：US09891985B1

公开(公告)日：2018-02-13

申请号：US14929275

申请日：2015-10-31

Applicant: Netronome Systems, Inc.

Inventor： Joseph M. Lamb ,  Benjamin D. Findlen

IPC: G06F11/10 ,  H03M13/09

CPC classification number: G06F11/1004 ,  H03M13/096

Abstract: A parser and checksum circuit includes a 256-bit data bus, IPV4, IPV6, TCP, and UDP state signal buses, a checksum summer and compare circuit, four 64-bit parsing circuits, a V6 extension processor, and a parse state context circuit. Each of the 64-bit parsing circuits includes two 32-bit parsing circuits. The data bus receives a data signal that is part of a packet. IPV4, IPV6, TCP, and UDP state signals are each configurable into 1-hot states where at most 1-bit is digital logic high. Each of the 1-hot states corresponds to a segment of a packet header of one of the IPV4, IPV6, TCP, and UDP protocols. Each 32-bit parsing circuit receives a 1-bit shifted version of the state signals received by the adjacent 32-bit parsing circuit and receives a portion of the data signal. State signals and the data signal portion are received in parallel during a single clock cycle.