EFFICIENT COMPLEX NETWORK TRAFFIC MANAGEMENT IN A NON-UNIFORM MEMORY SYSTEM
    1.
    发明申请
    EFFICIENT COMPLEX NETWORK TRAFFIC MANAGEMENT IN A NON-UNIFORM MEMORY SYSTEM 审中-公开
    在非均匀存储系统中的高效的复杂网络交通管理

    公开(公告)号:US20150309755A1

    公开(公告)日:2015-10-29

    申请号:US14631784

    申请日:2015-02-25

    Abstract: A network appliance includes a first processor, a second processor, a first storage device, and a second storage device. A first status information is stored in the first storage device. The first processor is coupled to the first storage device. A queue of data is stored in the second storage device. The first status information indicates if traffic data stored in the queue of data is permitted to be transmitted. The second processor is coupled to the second storage device. The first processor communicates with the second processor. The traffic data includes packet information. The first storage device is a high speed memory only accessible to the first processor. The second storage device is a high capacity memory accessible to multiple processors. The first status information is a permitted bit that indicates if the traffic data within the queue of data is permitted to be transmitted.

    Abstract translation: 网络设备包括第一处理器,第二处理器,第一存储设备和第二存储设备。 第一状态信息存储在第一存储装置中。 第一处理器耦合到第一存储设备。 数据队列存储在第二存储设备中。 第一状态信息指示是否允许发送存储在数据队列中的业务数据。 第二处理器耦合到第二存储设备。 第一处理器与第二处理器通信。 业务数据包括分组信息。 第一存储设备是只能由第一处理器访问的高速存储器。 第二存储设备是可由多个处理器访问的高容量存储器。 第一状态信息是指示允许发送数据队列内的业务数据的允许位。

    Efficient complex network traffic management in a non-uniform memory system

    公开(公告)号:US09304706B2

    公开(公告)日:2016-04-05

    申请号:US14631784

    申请日:2015-02-25

    Abstract: A network appliance includes a first processor, a second processor, a first storage device, and a second storage device. A first status information is stored in the first storage device. The first processor is coupled to the first storage device. A queue of data is stored in the second storage device. The first status information indicates if traffic data stored in the queue of data is permitted to be transmitted. The second processor is coupled to the second storage device. The first processor communicates with the second processor. The traffic data includes packet information. The first storage device is a high speed memory only accessible to the first processor. The second storage device is a high capacity memory accessible to multiple processors. The first status information is a permitted bit that indicates if the traffic data within the queue of data is permitted to be transmitted.

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