公开(公告)号：US20240095083A1

公开(公告)日：2024-03-21

申请号：US18174906

申请日：2023-02-27

Applicant: Nvidia Corporation

Inventor： Martin Stich ,  Rasmus Barringer ,  Robert Toth

IPC: G06F9/50

CPC classification number: G06F9/505 ,  G06F9/5033 ,  G06F9/5072

Abstract: Approaches for addressing issues associated with processing workloads that exhibit high divergence in execution and data access are provided. A plurality of workload items to be processed at least partially in parallel may be identified. Coherence information associated with the plurality of workload items may be determined. The plurality of workload items may be enqueued in a segmented queue. The plurality of workload items may be sorted based at least on a similarity of the coherence information. The sorted plurality of workload items may be stored to the queue. Using a set of processing units, the workload items in the queue may be processed at least partially in parallel according to an order of the sorting.