公开(公告)号：US08593345B2

公开(公告)日：2013-11-26

申请号：US13400390

申请日：2012-02-20

申请人： Paul A. Underbrink ,  Henry D. Falk ,  Steven A. Gronemeyer ,  Chittharanjan Dassannacharya ,  Charles P. Norman ,  Nicolas Vantalon ,  Vojislav Protic

发明人： Paul A. Underbrink ,  Henry D. Falk ,  Steven A. Gronemeyer ,  Chittharanjan Dassannacharya ,  Charles P. Norman ,  Nicolas Vantalon ,  Vojislav Protic

IPC分类号： G01S19/32

CPC分类号： G01S19/13 ,  G01S19/24 ,  G01S19/34 ,  G01S19/37 ,  H04B1/707 ,  H04B2201/70715

摘要： A signal processing system for processing satellite positioning signals is described. The system comprises at least one processor and a signal processor operating under a number of operational modes. The signal processor includes at least one of a signal processing subsystem, a fast Fourier transform (FFT) subsystem, and a memory subsystem that are each dynamically and independently configurable in response to the operational modes. Further, the system includes a controller that couples to control transfer of data among the signal processing subsystem and the FFT subsystem via the memory subsystem. Configurability of the memory subsystem includes configuring the memory subsystem into regions according to the operational modes where each region is accessible in one of a number of manners according to the operational modes.

摘要翻译： 描述了一种用于处理卫星定位信号的信号处理系统。 该系统包括在多种操作模式下操作的至少一个处理器和信号处理器。 信号处理器包括信号处理子系统，快速傅立叶变换（FFT）子系统和存储器子系统中的至少一个，每个动态和独立地可以响应于操作模式配置。 此外，该系统包括控制器，其经由存储器子系统耦合以控制信号处理子系统和FFT子系统之间的数据传送。 存储器子系统的可配置性包括根据操作模式将存储器子系统配置到区域中，根据操作模式，可以以多种方式之一访问每个区域。

公开(公告)号：US20110102258A1

公开(公告)日：2011-05-05

申请号：US10570833

申请日：2004-09-02

申请人： Paul A. Underbrink ,  Henry D. Falk ,  Steven A. Gronemeyer ,  Chittharanjan Dassannacharya ,  Charles P. Norman ,  Nicolas Vantalon ,  Vojislav Protic

发明人： Paul A. Underbrink ,  Henry D. Falk ,  Steven A. Gronemeyer ,  Chittharanjan Dassannacharya ,  Charles P. Norman ,  Nicolas Vantalon ,  Vojislav Protic

IPC分类号： G01S19/10 ,  G01S19/13 ,  G01S19/24

CPC分类号： H04B1/707 ,  G01S19/37 ,  H04B2201/70715

摘要： A signal processing system for processing satellite positioning signals is described. The system comprises at least one processor and a signal processor operating under a number of operational modes. The signal processor includes at last one of a signal processing subsystem, a fast Fourier transform (FFT) subsystem, and a memory subsystem that are each dynamically and independently configurable in response to the operational modes. Further, the system includes a controller that couples to control transfer of data among the signal processing subsystem and the FFT subsystem via the memory subsystem. Configurability of the memory subsystem includes configuring the memory subsystem into regions according to the operational modes where each region is accessible in one of a number of manners according to the operational modes.

摘要翻译： 描述了一种用于处理卫星定位信号的信号处理系统。 该系统包括在多种操作模式下操作的至少一个处理器和信号处理器。 信号处理器包括信号处理子系统，快速傅里叶变换（FFT）子系统和存储器子系统中的最后一个，每个动态和独立可配置以响应于操作模式。 此外，该系统包括控制器，其经由存储器子系统耦合以控制信号处理子系统和FFT子系统之间的数据传送。 存储器子系统的可配置性包括根据操作模式将存储器子系统配置到区域中，根据操作模式，可以以多种方式之一访问每个区域。

公开(公告)号：US20120313817A1

公开(公告)日：2012-12-13

申请号：US13400390

申请日：2012-02-20

申请人： Paul A. Underbrink ,  Henry D. Falk ,  Steven A. Gronemeyer ,  Chittharanjan A. Dasannacharya ,  Charles P. Norman ,  Nicolas Vantalon ,  Vojislav Protic

发明人： Paul A. Underbrink ,  Henry D. Falk ,  Steven A. Gronemeyer ,  Chittharanjan A. Dasannacharya ,  Charles P. Norman ,  Nicolas Vantalon ,  Vojislav Protic

IPC分类号： G01S19/32

CPC分类号： G01S19/13 ,  G01S19/24 ,  G01S19/34 ,  G01S19/37 ,  H04B1/707 ,  H04B2201/70715

摘要： A signal processing system for processing satellite positioning signals is described. The system comprises at least one processor and a signal processor operating under a number of operational modes. The signal processor includes at least one of a signal processing subsystem, a fast Fourier transform (FFT) subsystem, and a memory subsystem that are each dynamically and independently configurable in response to the operational modes. Further, the system includes a controller that couples to control transfer of data among the signal processing subsystem and the FFT subsystem via the memory subsystem. Configurability of the memory subsystem includes configuring the memory subsystem into regions according to the operational modes where each region is accessible in one of a number of manners according to the operational modes.

摘要翻译： 描述了一种用于处理卫星定位信号的信号处理系统。 该系统包括在多种操作模式下操作的至少一个处理器和信号处理器。 信号处理器包括信号处理子系统，快速傅立叶变换（FFT）子系统和存储器子系统中的至少一个，每个动态和独立地可以响应于操作模式配置。 此外，该系统包括控制器，其经由存储器子系统耦合以控制信号处理子系统和FFT子系统之间的数据传送。 存储器子系统的可配置性包括根据操作模式将存储器子系统配置到区域中，根据操作模式，可以以多种方式之一访问每个区域。

公开(公告)号：US08138972B2

公开(公告)日：2012-03-20

申请号：US10570833

申请日：2004-09-02

申请人： Paul A. Underbrink ,  Henry D. Falk ,  Steven A. Gronemeyer ,  Chittharanjan A. Dassannacharya ,  Charles P. Norman ,  Nicolas Vantalon ,  Vojislav Protic

发明人： Paul A. Underbrink ,  Henry D. Falk ,  Steven A. Gronemeyer ,  Chittharanjan A. Dassannacharya ,  Charles P. Norman ,  Nicolas Vantalon ,  Vojislav Protic

IPC分类号： G01S19/24

CPC分类号： H04B1/707 ,  G01S19/37 ,  H04B2201/70715

摘要： A signal processing system for processing satellite positioning signals is described. The system comprises at least one processor and a signal processor operating under a number of operational modes. The signal processor includes at least one of a signal processing subsystem, a fast Fourier transform (FFT) subsystem, and a memory subsystem that are each dynamically and independently configurable in response to the operational modes. Further, the system includes a controller that couples to control transfer of data among the signal processing subsystem and the FFT subsystem via the memory subsystem. Configurability of the memory subsystem includes configuring the memory subsystem into regions according to the operational modes where each region is accessible in one of a number of manners according to the operational modes.

摘要翻译： 描述了一种用于处理卫星定位信号的信号处理系统。 该系统包括在多种操作模式下操作的至少一个处理器和信号处理器。 信号处理器包括信号处理子系统，快速傅立叶变换（FFT）子系统和存储器子系统中的至少一个，每个动态和独立地可以响应于操作模式配置。 此外，该系统包括控制器，其经由存储器子系统耦合以控制信号处理子系统和FFT子系统之间的数据传送。 存储器子系统的可配置性包括根据操作模式将存储器子系统配置到区域中，根据操作模式，可以以多种方式之一访问每个区域。

公开(公告)号：US08321636B2

公开(公告)日：2012-11-27

申请号：US11369898

申请日：2006-03-06

申请人： Nicolas P. Vantalon ,  Steven A. Gronemeyer ,  Vojislav Protic

发明人： Nicolas P. Vantalon ,  Steven A. Gronemeyer ,  Vojislav Protic

IPC分类号： G06F13/12

CPC分类号： G06F12/0284 ,  G01S19/215 ,  G01S19/246 ,  G01S19/29 ,  G01S19/30 ,  G01S19/37 ,  G06F9/544 ,  G06F12/0223 ,  H04B1/7075 ,  H04B1/7097 ,  H04B1/7107 ,  H04B2201/70715

摘要： Memory reallocation and sharing among components of an electronic system is provided. The electronic system includes a first memory area coupled for access by a first processor via a first bus, and a second memory area coupled for access by a second processor via a second bus. An example system includes a central processor as the first processor and a digital signal processor as the second processor. The electronic system further includes memory configurations that support shared access of the second memory area by the first processor. Using shared access, the first processor can directly access the second memory via the first bus or indirectly access the second memory via the second bus and the second processor. The memory sharing also includes partitioning the shared memory to simultaneously provide the first processor with direct and indirect access to the shared memory.

摘要翻译： 提供电子系统组件之间的内存重新分配和共享。 电子系统包括第一存储器区域，其被耦合用于经由第一总线由第一处理器访问，第二存储器区域被耦合以经由第二总线由第二处理器访问。 示例系统包括作为第一处理器的中央处理器和作为第二处理器的数字信号处理器。 电子系统还包括支持第一处理器对第二存储器区域的共享访问的存储器配置。 使用共享访问，第一处理器可以经由第一总线直接访问第二存储器，或通过第二总线和第二处理器间接访问第二存储器。 存储器共享还包括划分共享存储器以同时向第一处理器提供对共享存储器的直接和间接访问。

公开(公告)号：US20060248289A1

公开(公告)日：2006-11-02

申请号：US11369898

申请日：2006-03-06

申请人： Nicolas Vantalon ,  Steven Gronemeyer ,  Vojislav Protic

发明人： Nicolas Vantalon ,  Steven Gronemeyer ,  Vojislav Protic

IPC分类号： G06F12/00

CPC分类号： G06F12/0284 ,  G01S19/215 ,  G01S19/246 ,  G01S19/29 ,  G01S19/30 ,  G01S19/37 ,  G06F9/544 ,  G06F12/0223 ,  H04B1/7075 ,  H04B1/7097 ,  H04B1/7107 ,  H04B2201/70715

摘要： Memory reallocation and sharing among components of an electronic system is provided. The electronic system includes a first memory area coupled for access by a first processor via a first bus, and a second memory area coupled for access by a second processor via a second bus. An example system includes a central processor as the first processor and a digital signal processor as the second processor. The electronic system further includes memory configurations that support shared access of the second memory area by the first processor. Using shared access, the first processor can directly access the second memory via the first bus or indirectly access the second memory via the second bus and the second processor. The memory sharing also includes partitioning the shared memory to simultaneously provide the first processor with direct and indirect access to the shared memory.

公开(公告)号：US07047368B2

公开(公告)日：2006-05-16

申请号：US10696522

申请日：2003-10-28

申请人： Nicolas P. Vantalon ,  Steven A. Gronemeyer ,  Vojislav Protic

发明人： Nicolas P. Vantalon ,  Steven A. Gronemeyer ,  Vojislav Protic

IPC分类号： G06F12/00

CPC分类号： G06F12/0284 ,  G01S19/215 ,  G01S19/246 ,  G01S19/29 ,  G01S19/30 ,  G01S19/37 ,  G06F9/544 ,  G06F12/0223 ,  H04B1/7075 ,  H04B1/7097 ,  H04B1/7107 ,  H04B2201/70715

摘要： Memory reallocation and sharing among components of an electronic system is provided. The electronic system includes a first memory area coupled for access by a first processor via a first bus, and a second memory area coupled for access by a second processor via a second bus. An example system includes a central processor as the first processor and a digital signal processor as the second processor. The electronic system further includes memory configurations that support shared access of the second memory area by the first processor. Using shared access, the first processor can directly access the second memory via the first bus or indirectly access the second memory via the second bus and the second processor. The memory sharing also includes partitioning the shared memory to simultaneously provide the first processor with direct and indirect access to the shared memory.

摘要翻译： 提供电子系统组件之间的内存重新分配和共享。 电子系统包括第一存储器区域，其被耦合用于经由第一总线由第一处理器访问，第二存储器区域被耦合以经由第二总线由第二处理器访问。 示例系统包括作为第一处理器的中央处理器和作为第二处理器的数字信号处理器。 电子系统还包括支持第一处理器对第二存储器区域的共享访问的存储器配置。 使用共享访问，第一处理器可以经由第一总线直接访问第二存储器，或通过第二总线和第二处理器间接访问第二存储器。 存储器共享还包括划分共享存储器以同时向第一处理器提供对共享存储器的直接和间接访问。

公开(公告)号：US20050050282A1

公开(公告)日：2005-03-03

申请号：US10696522

申请日：2003-10-28

申请人： Nicolas Vantalon ,  Steven Gronemeyer ,  Vojislav Protic

发明人： Nicolas Vantalon ,  Steven Gronemeyer ,  Vojislav Protic

IPC分类号： G01S1/00 ,  G06F9/46 ,  G06F12/02 ,  H04B1/707 ,  G06F12/00

CPC分类号： G06F12/0284 ,  G01S19/215 ,  G01S19/246 ,  G01S19/29 ,  G01S19/30 ,  G01S19/37 ,  G06F9/544 ,  G06F12/0223 ,  H04B1/7075 ,  H04B1/7097 ,  H04B1/7107 ,  H04B2201/70715

摘要： Memory reallocation and sharing among components of an electronic system is provided. The electronic system includes a first memory area coupled for access by a first processor via a first bus, and a second memory area coupled for access by a second processor via a second bus. An example system includes a central processor as the first processor and a digital signal processor as the second processor. The electronic system further includes memory configurations that support shared access of the second memory area by the first processor. Using shared access, the first processor can directly access the second memory via the first bus or indirectly access the second memory via the second bus and the second processor. The memory sharing also includes partitioning the shared memory to simultaneously provide the first processor with direct and indirect access to the shared memory.

摘要翻译： 提供电子系统组件之间的内存重新分配和共享。 电子系统包括第一存储器区域，其被耦合用于经由第一总线由第一处理器访问，第二存储器区域被耦合以经由第二总线由第二处理器访问。 示例系统包括作为第一处理器的中央处理器和作为第二处理器的数字信号处理器。 电子系统还包括支持第一处理器对第二存储器区域的共享访问的存储器配置。 使用共享访问，第一处理器可以经由第一总线直接访问第二存储器，或通过第二总线和第二处理器间接访问第二存储器。 存储器共享还包括划分共享存储器以同时向第一处理器提供对共享存储器的直接和间接访问。