公开(公告)号：US12019581B2

公开(公告)日：2024-06-25

申请号：US17936995

申请日：2022-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungjin Kim ,  Jinmyung Yoon ,  Youngmin Lee ,  Dasom Lee

IPC: G06F15/80 ,  G06F12/02 ,  G06F12/0806 ,  G06F12/1045 ,  G06F13/16 ,  G06F15/163 ,  G06F15/167

CPC classification number: G06F15/80 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0806 ,  G06F12/1054 ,  G06F13/1663 ,  G06F15/163 ,  G06F15/167 ,  G06F2212/68

Abstract: A multi-core processor includes a plurality of cores, a shared memory, a plurality of address allocators, and a bus. The shared memory has a message queue including a plurality of memory regions for transmitting messages between the plurality of cores. The plurality of address allocators are configured to, each time addresses in a predetermined range corresponding to a reference memory region among the plurality of memory regions are received from a corresponding core among the plurality of cores, control the plurality of memory regions to be accessed in sequence by applying an offset determined according to an access count of the reference memory region to the addresses in the predetermined range. The bus is configured to connect the plurality of cores, the shared memory, and the plurality of address allocators to one another.

公开(公告)号：US12019422B2

公开(公告)日：2024-06-25

申请号：US17082021

申请日：2020-10-28

Applicant: Kabushiki Kaisha Yaskawa Denki

Inventor： Masaomi Kudo ,  Takefumi Matsunaga ,  Hiroyuki Ishibashi ,  Yuki Yoshida

IPC: G05B19/042 ,  G05B19/05 ,  G06F3/06 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/109

CPC classification number: G05B19/0426 ,  G05B19/056 ,  G05B19/058 ,  G06F3/06 ,  G06F12/0284 ,  G06F12/1009 ,  G06F12/109 ,  G05B2219/25004

Abstract: A control device configured to control an industrial machine, the control device having: a plurality of memories including a first memory configured to hold data when a power supply is off and a second memory configured to inhibit data from being held when the power supply is off; and circuitry configured to: set, in each of a plurality of data units, an attribute indicating whether the data unit is to be held when the power supply is off; and set an address of each data unit such that each data unit is stored in one of the plurality of memories corresponding to the attribute.

公开(公告)号：US11941405B2

公开(公告)日：2024-03-26

申请号：US18227092

申请日：2023-07-27

Applicant: UNTETHER AI CORPORATION

Inventor： William Martin Snelgrove ,  Darrick John Wiebe

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/02 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F15/78 ,  G06N3/045 ,  G06N3/063

CPC classification number: G06F9/3887 ,  G06F9/3001 ,  G06F9/30101 ,  G06F12/0284 ,  G06F13/1668 ,  G06F13/287 ,  G06F13/4068 ,  G06F15/7821 ,  G06N3/045 ,  G06N3/063 ,  G06F2212/1028

Abstract: An example device includes a plurality of computational memory banks. Each computational memory bank of the plurality of computational memory banks includes an array of memory units and a plurality of processing elements connected to the array of memory units. The device further includes a plurality of single instruction, multiple data (SIMD) controllers. Each SIMD controller of the plurality of SIMD controllers is contained within at least one computational memory bank of the plurality of computational memory banks. Each SIMD controller is to provide instructions to the at least one computational memory bank.

公开(公告)号：US11907557B2

公开(公告)日：2024-02-20

申请号：US17681025

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Susanne M. Balle ,  Francesc Guim Bernat ,  Slawomir Putyrski ,  Joe Grecco ,  Henry Mitchel ,  Evan Custodio ,  Rahul Khanna ,  Sujoy Sen

IPC: G06F15/80 ,  G06F3/06 ,  G06F16/174 ,  G06F21/57 ,  G06F21/73 ,  G06F8/65 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/12 ,  H04L67/10 ,  G06F11/30 ,  G06F9/50 ,  H01R13/453 ,  G06F9/48 ,  G06F9/455 ,  H05K7/14 ,  H04L61/5007 ,  H04L67/63 ,  H04L67/75 ,  H03M7/30 ,  H03M7/40 ,  H04L43/08 ,  H04L47/20 ,  H04L47/2441 ,  G06F11/07 ,  G06F11/34 ,  G06F7/06 ,  G06T9/00 ,  H03M7/42 ,  H04L12/28 ,  H04L12/46 ,  G06F13/16 ,  G06F21/62 ,  G06F21/76 ,  H03K19/173 ,  H04L9/08 ,  H04L41/044 ,  H04L49/104 ,  H04L43/04 ,  H04L43/06 ,  H04L43/0894 ,  G06F9/38 ,  G06F12/02 ,  G06F12/06 ,  G06T1/20 ,  G06T1/60 ,  G06F9/54 ,  H04L67/1014 ,  G06F8/656 ,  G06F8/658 ,  G06F8/654 ,  G06F9/4401 ,  H01R13/631 ,  H04L47/78 ,  G06F16/28 ,  H04Q11/00 ,  G06F11/14 ,  H04L41/046 ,  H04L41/0896 ,  H04L41/142 ,  H04L9/40

CPC classification number: G06F3/0641 ,  G06F3/0604 ,  G06F3/065 ,  G06F3/067 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/0653 ,  G06F7/06 ,  G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F8/658 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/4401 ,  G06F9/45533 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/5005 ,  G06F9/505 ,  G06F9/5038 ,  G06F9/5044 ,  G06F9/5083 ,  G06F9/544 ,  G06F11/0709 ,  G06F11/079 ,  G06F11/0751 ,  G06F11/3006 ,  G06F11/3034 ,  G06F11/3055 ,  G06F11/3079 ,  G06F11/3409 ,  G06F12/0284 ,  G06F12/0692 ,  G06F13/1652 ,  G06F16/1744 ,  G06F21/57 ,  G06F21/6218 ,  G06F21/73 ,  G06F21/76 ,  G06T1/20 ,  G06T1/60 ,  G06T9/005 ,  H01R13/453 ,  H01R13/4536 ,  H01R13/4538 ,  H01R13/631 ,  H03K19/1731 ,  H03M7/3084 ,  H03M7/40 ,  H03M7/42 ,  H03M7/60 ,  H03M7/6011 ,  H03M7/6017 ,  H03M7/6029 ,  H04L9/0822 ,  H04L12/2881 ,  H04L12/4633 ,  H04L41/044 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/12 ,  H04L43/04 ,  H04L43/06 ,  H04L43/08 ,  H04L43/0894 ,  H04L47/20 ,  H04L47/2441 ,  H04L49/104 ,  H04L61/5007 ,  H04L67/10 ,  H04L67/1014 ,  H04L67/63 ,  H04L67/75 ,  H05K7/1452 ,  H05K7/1487 ,  H05K7/1491 ,  G06F11/1453 ,  G06F12/023 ,  G06F15/80 ,  G06F16/285 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2221/2107 ,  H04L41/046 ,  H04L41/0896 ,  H04L41/142 ,  H04L47/78 ,  H04L63/1425 ,  H04Q11/0005 ,  H05K7/1447 ,  H05K7/1492

Abstract: Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of each accelerator device. The compute engine is further to schedule the tasks to the one or more accelerator devices based on the job analysis and execute the tasks on the one or more accelerator devices for the parallelization of the multiple tasks to obtain an output of the job.

公开(公告)号：US20240054071A1

公开(公告)日：2024-02-15

申请号：US17819862

申请日：2022-08-15

Applicant: Intel Corporation

Inventor： KRYSTOF ZMUDZINSKI

IPC: G06F12/02 ,  G06F21/60 ,  H04L9/08 ,  G06F12/14

CPC classification number: G06F12/0284 ,  G06F21/602 ,  H04L9/0861 ,  G06F12/1408 ,  G06F2212/1052

Abstract: An apparatus comprises a hardware processor to define a linear address (LA) region outside an established address range for a secure enclave, generate, for the linear address (LA) region, a unique encryption key accessible only to the enclave, assign a key identifier to the unique encryption key, store the linear address (LA) region and the unique encryption key in an enclave control structure, and program the key identifier and the unique encryption key into a memory encryption circuitry.

公开(公告)号：US11886345B2

公开(公告)日：2024-01-30

申请号：US17820092

申请日：2022-08-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Burkhard Steinmacher-Burow

IPC: G06F12/0817 ,  G06F12/02 ,  G06F11/20 ,  G06F12/0808

CPC classification number: G06F12/0817 ,  G06F11/2033 ,  G06F12/0284 ,  G06F12/0292 ,  G06F12/0808

Abstract: Configuring an address-to-SC unit (A2SU) of each of a plurality of CPU chips based on a number of valid SC chips in the computer system is disclosed. The A2SU is configured to correlate each of a plurality of memory addresses with a respective one of the valid SC chips. In response to detecting a change in the number of valid SC chips, pausing operation of the computer system including operation of a cache of each of the plurality of CPU chips; while operation of the computer system is paused, reconfiguring the A2SU in each of the plurality of CPU chips based on the change in the number of valid SC chips; and in response to reconfiguring the A2SU, resuming operation of the computer system.

公开(公告)号：US20240004643A1

公开(公告)日：2024-01-04

申请号：US18463638

申请日：2023-09-08

Applicant: Aurora Labs Ltd.

Inventor： Zohar Fox

IPC: G06F8/658 ,  B60W50/04 ,  B60W50/02 ,  G06F21/57 ,  G06F11/14 ,  G06F9/445 ,  G06F12/02 ,  G06F8/656 ,  G06F8/654 ,  G06F16/188 ,  G06F9/4401 ,  G06F12/06 ,  G06F8/65 ,  G06F8/71 ,  G06F11/07 ,  G06F11/36 ,  G06F8/60 ,  G06F11/16

CPC classification number: G06F8/658 ,  B60W50/045 ,  B60W50/02 ,  B60W50/0205 ,  G06F21/57 ,  G06F21/572 ,  G06F11/1433 ,  G06F9/44521 ,  G06F12/0284 ,  G06F8/656 ,  G06F8/654 ,  G06F16/188 ,  G06F9/4401 ,  G06F9/445 ,  G06F12/0646 ,  G06F8/65 ,  G06F8/71 ,  G06F21/577 ,  B60W50/04 ,  G06F11/0721 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/3612 ,  G06F8/60 ,  B60W50/0225 ,  G06F11/0793 ,  G06F11/1629 ,  G06F2212/1044 ,  G06F2212/1056 ,  G06F2212/1008 ,  G06N20/00

Abstract: Disclosed embodiments relate to opportunistically updating Electronic Control Unit (ECU) software in a vehicle. Operations may include receiving, at a controller in a vehicle, a wireless transmission indicating a need to update software running on at least one ECU in the vehicle; monitoring an operational status of the vehicle to determine whether the vehicle is in a first mode of operation in which an ECU software update is prohibited; delaying the ECU software update when the operational status is prohibited; continuing to monitor the operational status of the vehicle to determine whether the vehicle is in a second mode of operation in which the ECU software update is permitted; and enabling updating of the at least one ECU with the delayed ECU software update when it is determined that the vehicle is in the second mode of operations.

公开(公告)号：US20230401159A1

公开(公告)日：2023-12-14

申请号：US18455479

申请日：2023-08-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anthony Asaro ,  Kevin Normoyle ,  Mark Hummel

IPC: G06F12/1036 ,  G06F12/08 ,  G06F12/06 ,  G06F12/02 ,  G06F12/109

CPC classification number: G06F12/1036 ,  G06F12/08 ,  G06F12/0646 ,  G06F12/0284 ,  G06F12/109 ,  G06F12/10

Abstract: A method and system for providing memory in a computer system. The method includes receiving a memory access request for a shared memory address from a processor, mapping the received memory access request to at least one virtual memory pool to produce a mapping result, and providing the mapping result to the processor.

公开(公告)号：US11822917B2

公开(公告)日：2023-11-21

申请号：US18053406

申请日：2022-11-08

Applicant: Aurora Labs Ltd.

Inventor： Zohar Fox

IPC: G06F8/658 ,  G06F11/16 ,  G06F9/44 ,  G06N20/00 ,  G06F8/654 ,  G06F9/455 ,  B60W50/04 ,  B60W50/02 ,  G06F21/57 ,  G06F11/14 ,  G06F9/445 ,  G06F12/02 ,  G06F8/656 ,  G06F16/188 ,  G06F9/4401 ,  G06F12/06 ,  G06F8/65 ,  G06F8/71 ,  G06F11/07 ,  G06F11/36 ,  G06F8/60

CPC classification number: G06F8/658 ,  B60W50/02 ,  B60W50/0205 ,  B60W50/0225 ,  B60W50/04 ,  B60W50/045 ,  G06F8/60 ,  G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F8/71 ,  G06F9/4401 ,  G06F9/445 ,  G06F9/44521 ,  G06F11/079 ,  G06F11/0721 ,  G06F11/0751 ,  G06F11/0793 ,  G06F11/1433 ,  G06F11/1629 ,  G06F11/3612 ,  G06F12/0284 ,  G06F12/0646 ,  G06F16/188 ,  G06F21/57 ,  G06F21/572 ,  G06F21/577 ,  B60W2050/021 ,  G06F8/66 ,  G06F2212/1008 ,  G06F2212/1044 ,  G06F2212/1056 ,  G06F2221/033 ,  G06N20/00

Abstract: Disclosed embodiments relate to identifying Electronic Control Unit (ECU) anomalies in a vehicle. Operations may include monitoring, in the vehicle, data representing real-time processing activity of the ECU; accessing, in the vehicle, historical data relating to processing activity of the ECU, the historical data representing expected processing activity of the ECU; comparing, in the vehicle, the real-time processing activity data with the historical data, to identify at least one anomaly in the real-time processing activity of the ECU; and implementing a control action for the ECU when the at least one anomaly is identified.

公开(公告)号：US20230305954A1

公开(公告)日：2023-09-28

申请号：US18202835

申请日：2023-05-26

Applicant: SK Hynix NAND Product Solutions Corp. (dba Solidigm)

Inventor： Mariusz Barczak

IPC: G06F12/02

CPC classification number: G06F12/0284 ,  G06F2212/1041 ,  G06F2212/1024

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to receive a first request to allocate a direct swap file associated with an application stored in a system memory on a persistent storage media, and map a linear and continuous space of the persistent storage media to the direct swap file associated with the application in response to the first request. Other embodiments are disclosed and claimed.