公开(公告)号：US20220317758A1

公开(公告)日：2022-10-06

申请号：US17220603

申请日：2021-04-01

Applicant: QUALCOMM INCORPORATED

Inventor： COLIN BEATON VERRILLI ,  Matthew SEVERSON

IPC: G06F1/3287 ,  G06F1/324 ,  G06F1/3296 ,  G01R21/133

Abstract: In each of two or more pipelined subsystems, the relative amount of time that the processing cores are idle may be determined. If the idle ratio is below a threshold, the clock frequency and voltage may be adjusted using dynamic clock and voltage scaling (DCVS) based on a power limit. However, if the idle ratio exceeds the threshold, the clock frequency and voltage may be decreased without regard to the power limit.