公开(公告)号：US20150277894A1

公开(公告)日：2015-10-01

申请号：US14307415

申请日：2014-06-17

Applicant: Qualcomm Incorporated

Inventor： EUGEN PIRVU ,  DHAMIM PACKER ALI ,  ASHUTOSH JAGDISH SHRIVASTAVA

IPC: G06F9/445 ,  G06F21/57

CPC classification number: G06F8/66 ,  G06F21/575

Abstract: A system and method for patching a boot sequence in a read-only memory. Patch instances are provided in an addressable memory. The patch instances are initially empty. The read-only memory includes a process that dynamically vectors to identified locations in a set of addressable memory locations in the addressable memory. Thereafter, the process returns to the next subsequent instruction following the patch instance. As corrections are required, the one or more patch instances are populated with one or more respective patches. The boot sequence is modified by inserting one or more patch indicators located where patches might need to be applied after a system-on-chip (SoC) is embodied in firmware. The patches, when defined, are populated with at least an encoded instruction type and an address. Accordingly, a patch is enabled in no more than three words.

Abstract translation: 用于在只读存储器中修补引导序列的系统和方法。 补丁实例在可寻址存储器中提供。 补丁实例最初为空。 只读存储器包括动态地向可寻址存储器中的一组可寻址存储器位置中的识别位置传送的过程。 此后，该过程返回到补丁实例之后的下一个后续指令。 当需要更正时，一个或多个补丁实例被填充有一个或多个相应的补丁。 通过在固件中体现片上系统（SoC）之后插入一个或多个补丁指示器来修改引导顺序，该补丁指示器位于需要应用补丁的位置。 补丁在定义时至少填充一个编码指令类型和地址。 因此，补丁的启用不超过三个字。

公开(公告)号：US20190034195A1

公开(公告)日：2019-01-31

申请号：US15660429

申请日：2017-07-26

Applicant: QUALCOMM INCORPORATED

Inventor： EUGEN PIRVU ,  DHAMIM PACKER ALI ,  DHAVAL PATEL ,  BHARGAV GURAPPADI

IPC: G06F9/445 ,  G06F12/06 ,  G06F15/78

Abstract: Systems, methods, and computer programs are disclosed for providing patchable read only memory (ROM) firmware. One method comprises receiving source code to be used as input for building a read only memory (ROM) image stored on a system on chip (SoC). One or more of a plurality of ROM functions in the source code to be made patchable are identified. The source code for the one or more of the plurality of ROM functions to be made patchable is modified by generating and inserting patching code into the corresponding source code. The patching code comprises a link to a fixed location in random access memory (RAM) for calling the corresponding function.

公开(公告)号：US20150242213A1

公开(公告)日：2015-08-27

申请号：US14187272

申请日：2014-02-23

Applicant: QUALCOMM INCORPORATED

Inventor： YANRU LI ,  DEXTER TAMIO CHUN ,  DHAMIM PACKER ALI ,  GREGORY AMERIADA UVIEGHARA ,  ZHONGZE WANG

IPC: G06F9/38

CPC classification number: G06F9/3802 ,  G06F8/66 ,  G06F12/0638

Abstract: Various embodiments of methods and systems for flexible read only memory (“ROM”) storage of coded instructions in a portable computing device (“PCD”) are disclosed. Because certain instructions and/or data associated with a primary boot loader (“PBL”) may be defective or in need of modification after manufacture of a mask ROM component, embodiments of flexible ROM storage (“FRS”) systems and methods use a closely coupled one-time programmable (“OTP”) memory component to store modified instructions and/or data. Advantageously, because the OTP memory component may be manufactured “blank” and programmed at a later time, modifications to code and/or data stored in an unchangeable mask ROM may be accomplished via pointers in fuses of a security controller that branch the request to the OTP and bypass the mask ROM.

Abstract translation: 公开了用于便携式计算设备（“PCD”）中的编码指令的灵活的只读存储器（“ROM”）存储的方法和系统的各种实施例。 由于与主引导加载程序（“PBL”）相关联的某些指令和/或数据在制造掩模ROM组件之后可能是有缺陷的或需要修改的，所以灵活的ROM存储（“FRS”）系统和方法的实施例使用紧密的 耦合的一次性可编程（“OTP”）存储器组件来存储经修改的指令和/或数据。 有利地，因为OTP存储器组件可以在稍后的时间被制造为“空白”并被编程，所以可以通过安全控制器的熔丝中的指针来实现对不可改变的掩模ROM中存储的代码和/或数据的修改，该安全控制器的熔丝将该请求分配到 OTP并绕过掩模ROM。

公开(公告)号：US20190080082A1

公开(公告)日：2019-03-14

申请号：US15699646

申请日：2017-09-08

Applicant: QUALCOMM INCORPORATED

Inventor： MAMTA DESAI ,  ASHUTOSH SHRIVASTAVA ,  DHAMIM PACKER ALI

IPC: G06F21/52 ,  G06F21/80

CPC classification number: G06F21/52 ,  G06F7/582 ,  G06F21/575 ,  G06F21/80 ,  G06F2221/034

Abstract: Systems and methods are disclosed for providing stack overflow protection on a system on chip via a hardware write-once register. An exemplary embodiment of an system on chip comprises a hardware write-once register, a boot processor, and one or more processor subsystems. The boot processor is configured to execute a read only memory (ROM) image which initializes the hardware write-once register with a first numeric value in response to the system on chip being powered on. The one or more processor subsystems have an associated software image configured to use the first numeric value in the hardware write-once register as a stack canary value to combat stack overflow attacks.

公开(公告)号：US20180365425A1

公开(公告)日：2018-12-20

申请号：US15624612

申请日：2017-06-15

Applicant: QUALCOMM INCORPORATED

Inventor： DHAMIM PACKER ALI ,  JEFFREY SHABEL ,  YANRU LI ,  ASHUTOSH SHRIVASTAVA

IPC: G06F21/57 ,  G06F9/44

Abstract: Systems, methods, and computer programs are disclosed for securely booting a system on chip. One embodiment is a system comprising a system on chip (SoC) and a virtual collated internal memory pool (VCIMP). The SoC comprises a bootable processing device having a first internal memory, a read only memory (ROM), and one or more bootable processing subsystems each having a dedicated internal memory. The bootable processing device is configured to execute a bootloader in the ROM. The VCIMP provides time-shared control and access to the one or more bootable processing subsystems during execution of a boot sequence. The VCIMP comprises a contiguous logical-to-physical address mapping of the first internal memory residing on the bootable processing device and the dedicated internal memories residing on the corresponding one or more bootable processing subsystems.

公开(公告)号：US20150149810A1

公开(公告)日：2015-05-28

申请号：US14139704

申请日：2013-12-23

Applicant: Qualcomm Incorporated

Inventor： DHAMIM PACKER ALI ,  TOM C. WANG ,  SHA LIU ,  SREENIVASULU REDDY CHALAMCHARLA

IPC: G06F11/14

CPC classification number: G06F11/1441 ,  G06F11/1492 ,  G06F11/2236

Abstract: A power management mechanism maintains power to a processor and an integrated memory. Read-only logic and a cache are also provided. At power on, the read-only logic configures the cache as an internal memory and loads executable instructions in the cache. A copy of the executable instructions is stored in the internal memory. A branch instruction is also stored. Thereafter, the processor uses the copy of the executable instructions and present status information. The processor is programmed to issue a reset signal when a failure is detected. The read-only logic responds to the reset signal by going to the branch instruction in the internal memory, which directs the processor to use the copy of the executable instructions and status information in the internal memory circuit. The operating state is restored and the processor is instructed to execute the next instruction in the copy of executable instructions.

Abstract translation: 电源管理机构维持处理器和集成存储器的电源。 还提供只读逻辑和缓存。 上电时，只读逻辑将高速缓存配置为内部存储器，并在缓存中加载可执行指令。 可执行指令的副本存储在内部存储器中。 还存储分支指令。 此后，处理器使用可执行指令的副本并呈现状态信息。 处理器被编程为在检测到故障时发出复位信号。 只读逻辑通过转到内部存储器中的分支指令来响应复位信号，这引导处理器使用内部存储器电路中的可执行指令和状态信息的副本。 恢复操作状态，并指示处理器执行可执行指令副本中的下一条指令。