公开(公告)号：US20170277461A1

公开(公告)日：2017-09-28

申请号：US15081915

申请日：2016-03-27

Applicant: QUALCOMM INCORPORATED

Inventor： YANRU LI ,  DEXTER TAMIO CHUN ,  ALAIN ARTIERE

IPC: G06F3/06 ,  G11C11/406 ,  G06F12/08

CPC classification number: G06F3/0625 ,  G06F1/3275 ,  G06F3/0611 ,  G06F3/0653 ,  G06F3/0685 ,  G06F12/0862 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/222 ,  G06F2212/602 ,  G11C11/40607 ,  Y02D10/13

Abstract: Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem adjusts access to the DRAM based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients.

公开(公告)号：US20170162235A1

公开(公告)日：2017-06-08

申请号：US14957045

申请日：2015-12-02

Applicant: QUALCOMM INCORPORATED

Inventor： SUBRATO DE ,  RICHARD STEWART ,  DEXTER TAMIO CHUN

IPC: G11C7/10 ,  G06F12/06 ,  G06F3/06 ,  G06F13/16

CPC classification number: G11C7/1072 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0685 ,  G06F12/0607 ,  G06F12/10 ,  G06F12/1027 ,  G06F13/1657 ,  G06F2212/657 ,  Y02D10/13 ,  Y02D10/14

Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power/performance optimization. One such method comprises configuring an interleaved zone for relatively higher performance tasks, a linear address zone for relatively lower power tasks, and a mixed interleaved-linear zone for tasks with intermediate performance requirements. A boundary is defined among the different zones using a sliding threshold address. The zones may be dynamically adjusted, and/or new zones dynamically created, by changing the sliding address in real-time based on system goals and application performance preferences. A request for high performance memory is allocated to a zone with lower power that minimally supports the required performance, or may be allocated to a low power memory zone with lower than required performance if the system parameters indicate a need for aggressive power conservation. Pages may be migrated between zones in order to free a memory device for powering down.

公开(公告)号：US20170123988A1

公开(公告)日：2017-05-04

申请号：US14929083

申请日：2015-10-30

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  YANRU LI

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0246 ,  G06F12/0804 ,  G06F2212/1016 ,  G06F2212/6026 ,  G06F2212/7203

Abstract: Systems and methods for improved flash memory performance in a portable computing device are presented. In a method, a value N corresponding to an amount of prefetch data to be retrieved from the flash memory is determined. An access request for a flash memory is received at a cache controller in communication with a cache memory. A determination is made whether the access request for the flash memory corresponds to a portion of data stored in the cache memory. If the access request for the flash memory corresponds to the portion of data, the portion of data is returned in response to the access request. Otherwise, an N amount of prefetch data is retrieved from the flash memory and stored in the cache memory. The value N is incremented based on a cache hit percentage for the cache memory.

公开(公告)号：US20170108914A1

公开(公告)日：2017-04-20

申请号：US14885803

申请日：2015-10-16

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  YANRU LI ,  BOHUSLAV RYCHLIK

IPC: G06F1/32 ,  G06F12/06 ,  H04W52/02

CPC classification number: G06F1/3287 ,  G06F12/0607 ,  G06F12/0623 ,  G06F2212/1016 ,  G06F2212/1028 ,  H04W52/0261 ,  Y02D10/13 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/168

Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method comprises configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance tasks, and the linear region comprises a linear address space for relatively lower power tasks. A boundary is defined between the linear region and the interleaved region using a sliding threshold address. A request is received from a process for a virtual memory page. The request comprises a preference for power savings or performance. The virtual memory page is assigned to a free physical page in the linear region or the interleaved region based on the preference for power savings or performance using the sliding threshold address.

公开(公告)号：US20170371812A1

公开(公告)日：2017-12-28

申请号：US15193423

申请日：2016-06-27

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN

IPC: G06F13/16 ,  G06F13/40 ,  G06F3/06

CPC classification number: G06F13/1678 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0607 ,  G06F13/4068 ,  G06F2213/0038

Abstract: A system for providing odd modulus memory channel interleaving may include a dynamic random access memory (DRAM) system and a system on chip (SoC). The SoC comprises a first memory controller, a second memory controller, and a symmetric memory channel interleaver. The first memory controller is electrically coupled to a first DRAM module via a first memory bus. The second memory controller is electrically coupled to a second DRAM module and a third DRAM module via a second memory bus. The symmetric memory channel interleaver is configured to uniformly distribute DRAM traffic to the first memory controller and the second memory controller. The first memory controller provides a first interleaved channel to the first DRAM module via the first memory bus. The second memory controller provides a second interleaved channel to the second DRAM module via upper address bits on the second memory bus.

公开(公告)号：US20170262367A1

公开(公告)日：2017-09-14

申请号：US15068184

申请日：2016-03-11

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  YANRU LI ,  JAVID JAFFARI ,  AMIN ANSARI

IPC: G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0284 ,  G06F12/0292 ,  G06F12/0607 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1081 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/502 ,  G06F2212/657 ,  G06F2212/7201 ,  G11C7/1075 ,  G11C8/12

Abstract: Systems, methods, and computer programs are disclosed for allocating memory in a hybrid parallel/serial memory system. One method comprises configuring a memory address map for a multi-rank memory system with a dedicated serial access region in a first memory rank and a dedicated parallel access region in a second memory rank. A request is received for a virtual memory page. If the request comprises a performance hint, the virtual memory page is selectively assigned to a free physical page in the dedicated serial access in the first memory rank and the dedicated parallel access region in the second memory rank.

公开(公告)号：US20170038805A1

公开(公告)日：2017-02-09

申请号：US14818180

申请日：2015-08-04

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN

IPC: G06F1/20 ,  G06F3/06

CPC classification number: G06F1/206 ,  G06F1/203 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0673 ,  G11C7/04

Abstract: Systems, methods, and computer programs, embodied in or as a memory management module, are disclosed for thermally controlling memory to increase its performance. One exemplary embodiment includes a memory, one or more processors, and a thermoelectric cooling device. The one or more processors access the memory via a memory controller electrically coupled to the memory. The thermoelectric cooling device is configured to thermally control the memory in response to a predicted change in temperature of the memory.

Abstract translation: 公开了体现在或作为存储器管理模块的系统，方法和计算机程序，用于热控制存储器以增加其性能。 一个示例性实施例包括存储器，一个或多个处理器和热电冷却装置。 一个或多个处理器通过电耦合到存储器的存储器控​​制器访问存储器。 热电冷却装置被配置为响应于预测的存储器的温度变化热控制存储器。

公开(公告)号：US20170003887A1

公开(公告)日：2017-01-05

申请号：US14791340

申请日：2015-07-03

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN

IPC: G06F3/06 ,  G11C11/56

CPC classification number: G06F3/0608 ,  G06F3/0661 ,  G06F3/0679 ,  G06F11/1072 ,  G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7204 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642

Abstract: Systems, methods, and computer programs are disclosed for providing compressed data storage using non-power-of-two flash cell mapping. One embodiment of a method comprises receiving one or more compressed logical pages to be stored in a NAND flash memory. Binary data in the one or more logical pages is transformed to a quinary representation. The quinary representation comprises a plurality of quinary bits. A binary representation of each of the plurality of quinary bits is transmitted to the NAND flash memory. The binary representation of each of the plurality of quinary bits is converted to a quinary voltage for a corresponding cell in a physical page in the NAND flash memory.

Abstract translation: 公开了系统，方法和计算机程序，用于使用非二功能闪存单元映射提供压缩数据存储。 一种方法的一个实施例包括接收要存储在NAND闪速存储器中的一个或多个压缩逻辑页面。 一个或多个逻辑页面中的二进制数据被转换为五进制表示。 五进制表示包括多个五进制位。 多个五进制位中的每一个的二进制表示被发送到NAND闪速存储器。 多个Quinary位中的每一个的二进制表示被转换为NAND闪速存储器中的物理页面中的对应单元的二次电压。

公开(公告)号：US20160054928A1

公开(公告)日：2016-02-25

申请号：US14464598

申请日：2014-08-20

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  SURYANARAYANA CHINA CHITTULURI ,  YANRU LI

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F3/0607 ,  G06F3/0631 ,  G06F3/0665 ,  G06F3/0683 ,  G06F12/0246 ,  G06F12/06 ,  G06F12/10 ,  G06F13/1684 ,  G06F2212/1048 ,  G06F2212/152 ,  G06F2212/171 ,  G06F2212/206 ,  G06F2212/214 ,  G06F2212/261 ,  G06F2212/654 ,  G06F2212/7201

Abstract: Systems and methods are disclosed for expanding memory for a system on chip (SoC). A memory card is loaded in an expandable memory socket electrically and is coupled to a system on chip (SoC) via an expansion bus. The memory card comprises a first volatile memory device. In response to detecting the memory card, an expanded virtual memory map is configured. The expanded virtual memory map comprises a first virtual memory space associated the first volatile memory device and a second virtual memory space associated with a second volatile memory device electrically coupled to the SoC via a memory bus. One or more peripheral images associated with the second virtual memory space are relocated to a first portion of the first virtual memory space. A second portion of the first virtual memory space is configured as a block device for performing swap operations associated with the second virtual memory space.

Abstract translation: 公开了用于扩展片上系统（SoC）的存储器的系统和方法。 存储卡电气地装载在可扩展存储器插槽中，并通过扩展总线耦合到片上系统（SoC）。 存储卡包括第一易失性存储器件。 响应于检测到存储卡，配置扩展的虚拟存储器映射。 扩展的虚拟存储器映射包括与第一易失性存储器设备相关联的第一虚拟存储器空间和与经由存储器总线电耦合到SoC的第二易失性存储器设备相关联的第二虚拟存储器空间。 与第二虚拟存储器空间相关联的一个或多个周边图像被重新定位到第一虚拟存储器空间的第一部分。 第一虚拟存储器空间的第二部分被配置为用于执行与第二虚拟存储器空间相关联的交换操作的块设备。

公开(公告)号：US20170277460A1

公开(公告)日：2017-09-28

申请号：US15081914

申请日：2016-03-27

Applicant: QUALCOMM INCORPORATED

Inventor： YANRU LI ,  DEXTER TAMIO CHUN ,  ALAIN ARTIERI

IPC: G06F3/06 ,  G11C11/406 ,  G11C7/10 ,  G06F12/08

CPC classification number: G06F1/3296 ,  G06F1/324 ,  G06F1/3275 ,  G06F12/0862 ,  G06F13/1689 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/222 ,  G06F2212/602 ,  G11C11/40607 ,  G11C2211/4067 ,  Y02D10/14

Abstract: Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem controls a DDR clock frequency based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients.