公开(公告)号：US12210958B2

公开(公告)日：2025-01-28

申请号：US16137491

申请日：2018-09-20

Applicant: QUALCOMM Incorporated

Inventor： Aaron Lamb ,  Rexford Hill ,  Amin Ansari

IPC: G06N3/063 ,  G06F7/544 ,  G06N3/045 ,  G06N3/084 ,  G06N3/044 ,  G06N3/047

Abstract: The present disclosure describes methods, computer-readable media, and apparatuses for operating neural networks. For example, a first apparatus may receive a set of sparse weight vectors. The first apparatus may compress the set of sparse weight vectors to produce a compressed set of sparse weight vectors. The first apparatus may operate a neural network based on the compressed set of sparse weight vectors. In another example, a second apparatus may receive a set of sparse weight vectors. The second apparatus may perform a sparse computation based on the set of sparse weight vectors, and the performance of the sparse computation may produce one or more partial sums. The second apparatus may operate a neural network based at least in part on the one or more partial sums.

公开(公告)号：US11586417B2

公开(公告)日：2023-02-21

申请号：US16147297

申请日：2018-09-28

Applicant: QUALCOMM Incorporated

Inventor： Rexford Hill ,  Aaron Lamb ,  Michael Goldfarb ,  Amin Ansari ,  Christopher Lott

IPC: G06F7/544 ,  G06F5/06 ,  G06N3/063

Abstract: A method of exploiting activation sparsity in deep neural networks is described. The method includes retrieving an activation tensor and a weight tensor where the activation tensor is a sparse activation tensor. The method also includes generating a compressed activation tensor comprising non-zero activations of the activation tensor, where the compressed activation tensor has fewer columns than the activation tensor. The method further includes processing the compressed activation tensor and the weight tensor to generate an output tensor.

公开(公告)号：US10037306B2

公开(公告)日：2018-07-31

申请号：US15255015

申请日：2016-09-01

Applicant: QUALCOMM Incorporated

Inventor： Dexu Lin ,  Edward Liao ,  Somdeb Majumdar ,  Aaron Lamb ,  Karamvir Chatha

IPC: G06F1/02 ,  G06F17/17

CPC classification number: G06F17/17 ,  G06F7/544 ,  G06F2207/5354 ,  G06N3/0481 ,  G06N3/063

Abstract: Computing a non-linear function ƒ(x) in hardware or embedded systems can be complex and resource intensive. In one or more aspects of the disclosure, a method, a computer-readable medium, and an apparatus are provided for computing a non-linear function ƒ(x) accurately and efficiently in hardware using look-up tables (LUTs) and interpolation or extrapolation. The apparatus may be a processor. The processor computes a non-linear function ƒ(x) for an input variable x, where ƒ(x)=g(y(x),z(x)). The processor determines an integer n by determining a position of a most significant bit (MSB) of an input variable x. In addition, the processor determines a value for y(x) based on a first look-up table and the determined integer n. Also, the processor determines a value for z(x) based on n and the input variable x, and based on a second look-up table. Further, the processor computes ƒ(x) based on the determined values for y(x) and z(x).