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    Digital signal processing device
    1.
    发明授权
    Digital signal processing device 有权

    公开(公告)号：US12124815B2

    公开(公告)日：2024-10-22

    申请号：US17747101

    申请日：2022-05-18

    Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

    Inventor： Pierre Gobin ,  Jeremy Ribeiro De Freitas

    IPC: G06F7/548 ,  G06F7/523 ,  G06F7/544

    CPC classification number: G06F7/544 ,  G06F7/523

    Abstract: A digital signal processor includes K first electronic circuits. The first inputs receive K groups of G successive coefficients of a polynomial. The polynomial are of degree N with N+1 coefficients, where K is a sub-multiple of N+1 greater than or equal to two and G is equal to (N+1)/K. The first electronic circuits are configured to simultaneously implement K respective Horner methods and deliver K output results. A second electronic circuit includes a first input configured to successively receive the output results of the first electronic circuits starting with the output result of the first electronic circuit having processed the highest rank coefficient of the coefficients. A second input is configured to receive a variable X and the second electronic circuit is configured to implement a Horner method and deliver a value of the polynomial for the variable X on the output of the second electronic circuit.

    Secure computation apparatus, secure computation method, and program
    3.
    发明授权
    Secure computation apparatus, secure computation method, and program 有权

    公开(公告)号：US11934564B2

    公开(公告)日：2024-03-19

    申请号：US17790769

    申请日：2020-01-20

    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION

    Inventor： Dai Ikarashi

    IPC: G06F21/00 ,  G06F7/544 ,  G06F21/71

    CPC classification number: G06F21/71 ,  G06F7/544

    Abstract: A secret share value [q] of a quotient q of a/p is obtained through secure computation using a secret share value [a] and a modulus p and [a/d0]=[(a+qp)/d0]−[q]p/d0, . . . , [a/dn−1]=[(a+qp)/dn−1]−[q]p/dn−1 are obtained and output through secure computation using secret share values [a] and [q], divisors d0, . . . , dn−1, and a modulus p. Here, [μ] is a secret share value of μ, a is a real number, n is an integer equal to or greater than 2, d0, . . . , dn−1 are divisors of real numbers, p is a modulus of a positive integer, and q is a quotient of a positive integer.

    Electronic device, input-data processing method, and storage medium
    4.
    发明授权
    Electronic device, input-data processing method, and storage medium 有权

    公开(公告)号：US11886834B2

    公开(公告)日：2024-01-30

    申请号：US17532762

    申请日：2021-11-22

    Applicant: CASIO COMPUTER CO., LTD.

    Inventor： Hiroaki Yoshizawa ,  Hironori Yoshikawa

    IPC: G06F7/544 ,  G06F3/0489

    CPC classification number: G06F7/544 ,  G06F3/0489

    Abstract: An electronic device including a processor configured to execute a program stored in a memory, in which the processor executes input-screen display processing of causing a display to display an input screen, in order to accept input of data for a certain item, executes, when the input of the data for the certain item is accepted by a first method during display of the input screen, default-value setting processing of setting the data as a default value for the certain item, and executes data processing with the data, and executes, when the input of the data for the certain item is accepted by a second method during display of the input screen, default-value non-setting processing of not setting the data as the default value, and executes the data processing with the data.

    Edge Device for Executing a Lightweight Pattern-Aware generative Adversarial Network
    6.
    发明公开
    Edge Device for Executing a Lightweight Pattern-Aware generative Adversarial Network 审中-公开

    公开(公告)号：US20230148015A1

    公开(公告)日：2023-05-11

    申请号：US17519589

    申请日：2021-11-05

    Applicant: Ceremorphic, Inc.

    Inventor： Manmohan TRIPATHI ,  Chandrajit PAL ,  Govardhan MATTELA

    IPC: G06N20/00 ,  G06F7/544

    CPC classification number: G06N20/00 ,  G06F7/544

    Abstract: In some embodiments, an edge device is configured to execute machine learning procedures with a sparse dataset. The edge device includes at least (1) one or more sensor interfaces, (2) one or more microcontrollers (MCUs), and one or more memories in communication with the one or more microcontrollers. The one or more memories contain one or more executable instructions that cause the one or more microcontrollers to perform operations that include at least: (a) receiving one or more batches of real-time sensor data via the one or more sensor interfaces, the one or more batches defining the sparse dataset, and creating one or more batches of augmented data with the one or more batches of real-time sensor data and one or more batches of generated synthetic data. In some embodiments the edge device is a resource-constrained edge device.

    FPGA Math Block with Dedicated Connections
    7.
    发明申请
    FPGA Math Block with Dedicated Connections 审中-公开

    公开(公告)号：US20190190522A1

    公开(公告)日：2019-06-20

    申请号：US16177244

    申请日：2018-10-31

    Applicant: Microsemi SoC Corp.

    Inventor： Jonathan W. Greene ,  Fei Li

    IPC: H03K19/177 ,  G06F7/544

    CPC classification number: H03K19/17728 ,  G06F7/544 ,  H03K19/17736

    Abstract: An architecture in a user-programmable integrated circuit includes a hard logic block having inputs and outputs, a first group of user-configurable general-purpose routing resources coupled to first selected ones of the inputs of the hard logic block, a soft logic block having inputs and outputs, first selected ones of the inputs of the soft logic block coupled to the first group of user-configurable general-purpose routing resources, first selected ones of the outputs of the soft logic block having dedicated connections to second selected ones of the inputs to the hard logic block, and a second group of user-configurable general-purpose routing resources coupled to second selected ones of the outputs of the soft logic block and to first selected ones of the outputs of the hard logic block.

    Configurable Processor with In-Package Look-Up Table
    8.
    发明申请
    Configurable Processor with In-Package Look-Up Table 审中-公开

    公开(公告)号：US20190114138A1

    公开(公告)日：2019-04-18

    申请号：US16203599

    申请日：2018-11-28

    Applicant: Guobiao ZHANG

    Inventor： Guobiao ZHANG

    IPC: G06F7/498 ,  G06F7/544

    CPC classification number: G06F7/4988 ,  G06F7/544 ,  H03K19/17728

    Abstract: A configurable processor comprises a memory die and a logic die. The memory die comprises a programmable memory array for storing a look-up table (LUT) for a mathematical function, while the logic die comprises an arithmetic logic circuit (ALC) for performing at least an arithmetic operation on selected data from the LUT, wherein said mathematical function includes more operation than the arithmetic operations performable by the ALC. Complex mathematical functions can be implemented and configured.

    Calculating Normalized Metrics
    9.
    发明申请
    Calculating Normalized Metrics 审中-公开

    公开(公告)号：US20180196637A1

    公开(公告)日：2018-07-12

    申请号：US15404599

    申请日：2017-01-12

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Gabriel DAYAN ,  Eli REVACH ,  Pavel DANICHEV ,  Avihay MOR

    IPC: G06F5/01 ,  G06F17/18

    CPC classification number: G06F5/01 ,  G06F7/544 ,  G06F17/18

    Abstract: Examples relate to calculating normalize metrics. The examples disclosed herein calculate respective normalized first metric values for each of a plurality of first metric values that are on a time scale and respective normalized second metric values for each of the plurality of raw second metric values that are on the time scale, where the plurality of first metric values are associated with a first metric, and the plurality of second metric values are associated with a second metric. An extremum of the normalized first metric value and the normalized second metric value at each time of the time scale is averaged to calculate a plurality of extremum baseline values. Examples herein calculate a plurality of sleeve values of the plurality of extremum baseline values based on a standard deviation of the plurality of extremum baseline values.

    PERFORM SIGN OPERATION DECIMAL INSTRUCTION
    10.
    发明申请
    PERFORM SIGN OPERATION DECIMAL INSTRUCTION 审中-公开

    公开(公告)号：US20180095727A1

    公开(公告)日：2018-04-05

    申请号：US15806836

    申请日：2017-11-08

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Jonathan D. Bradbury ,  Reid T. Copeland ,  Silvia Melitta Mueller ,  Timothy J. Slegel

    IPC: G06F7/544

    CPC classification number: G06F7/544 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30094

    Abstract: An instruction to perform a sign operation of a plurality of sign operations configured for the instruction. The instruction is executed, and the executing includes selecting at least a portion of an input operand as a result to be placed in a select location. The selecting is based on a control of the instruction, in which the control indicates a user-defined size of the input operand to be selected as the result. A sign of the result is determined based on a plurality of criteria, including a value of the result, obtained based on the control of the instruction, having a first particular relationship or a second particular relationship with respect to a selected value. The result and the sign are stored in the select location to provide a signed output to be used in processing within the computing environment.

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