公开(公告)号：US12255661B1

公开(公告)日：2025-03-18

申请号：US18537304

申请日：2023-12-12

Applicant: QUALCOMM Incorporated

Inventor： Julian Puscar ,  Burcin Serter Ergun ,  Brett Patrick Delaney ,  Zhiqin Chen

IPC: H03L7/095 ,  H03L7/18

Abstract: A method for calibrating a phase locked loop (PLL) includes counting cycles of an output clock signal generated by the PLL until early phase lock signal is asserted when the cycles of the output clock signal counted within a first duration of time differ from a first target value by no more than a first maximum difference, counting cycles of the output clock signal until final phase lock signal is asserted when the cycles of the output clock signal counted within a second duration of time differ from a second target value by no more than a second maximum difference, the second duration of time being greater than the first duration of time, and using the output clock signal to control an operation in a physical layer circuit of a communication interface after the early phase lock signal is asserted and before the final phase lock signal is asserted.