公开(公告)号：US11764795B2

公开(公告)日：2023-09-19

申请号：US17537264

申请日：2021-11-29

Applicant: QUALCOMM Incorporated

Inventor： Burcin Serter Ergun ,  Julian Puscar ,  Zhiqin Chen ,  Dewanshu Chhagan Sewake

IPC: H03D3/24 ,  H03L7/197 ,  H03L7/08 ,  H03L7/089 ,  H03L7/099 ,  H04L7/00

CPC classification number: H03L7/1974 ,  H03L7/0807 ,  H03L7/0891 ,  H03L7/099 ,  H04L7/0079

Abstract: A phase locked loop (PLL) method includes generating a first signal based on a comparison of a phase of a reference clock or signal to a phase of a feedback clock; generating an output clock based on the first signal; generating an intermediate feedback clock including frequency dividing the output clock; fractionally frequency dividing the intermediate feedback clock based on a digital control signal to generate the feedback clock; and generating the digital control signal based on a sampling clock having a frequency greater than a frequency of the feedback clock. In one implementation, a PLL includes a frequency multiplier to generate the sampling clock based on the feedback clock. In another implementation, a PLL uses the intermediate feedback clock as the sampling clock.

公开(公告)号：US12255661B1

公开(公告)日：2025-03-18

申请号：US18537304

申请日：2023-12-12

Applicant: QUALCOMM Incorporated

Inventor： Julian Puscar ,  Burcin Serter Ergun ,  Brett Patrick Delaney ,  Zhiqin Chen

IPC: H03L7/095 ,  H03L7/18

Abstract: A method for calibrating a phase locked loop (PLL) includes counting cycles of an output clock signal generated by the PLL until early phase lock signal is asserted when the cycles of the output clock signal counted within a first duration of time differ from a first target value by no more than a first maximum difference, counting cycles of the output clock signal until final phase lock signal is asserted when the cycles of the output clock signal counted within a second duration of time differ from a second target value by no more than a second maximum difference, the second duration of time being greater than the first duration of time, and using the output clock signal to control an operation in a physical layer circuit of a communication interface after the early phase lock signal is asserted and before the final phase lock signal is asserted.