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    METHODS AND APPARATUSES FOR EXTENDED CURRENT LIMIT FOR POWER REGULATION
    2.
    发明申请
    METHODS AND APPARATUSES FOR EXTENDED CURRENT LIMIT FOR POWER REGULATION 有权

    公开(公告)号：US20210294369A1

    公开(公告)日：2021-09-23

    申请号：US17207478

    申请日：2021-03-19

    Applicant: QUALCOMM Incorporated

    Inventor： Marko KOSKI ,  Edgar Marti-Arbona ,  Gordon Lee ,  Anish Muttreja ,  Ravi Jenkal

    IPC: G05F1/573 ,  G05F1/56

    Abstract: A method and apparatuses for power regulation using an extended current limit are disclosed. The power regulator detects an occurrence of an output current of the regulator exceeding a first current limit, triggers an extended current limit timer based on the detected occurrence, regulates the output current according to a second current limit higher than the first current limit based on a duration of the extended current limit timer, and regulates the output current according to the first current limit based on an expiration of the duration of the extended current limit timer.

    VOLTAGE REGULATOR OVER-CURRENT PROTECTION
    4.
    发明申请
    VOLTAGE REGULATOR OVER-CURRENT PROTECTION 审中-公开
    电压稳压器过流保护

    公开(公告)号：US20140292292A1

    公开(公告)日：2014-10-02

    申请号：US14151725

    申请日：2014-01-09

    Applicant: QUALCOMM Incorporated

    Inventor： Marko KOSKI

    IPC: H02H7/12

    CPC classification number: H02H7/1213 ,  H02M1/32 ,  H02M3/1588 ,  Y02B70/1466

    Abstract: Exemplary embodiments are related to a buck regulator. A buck regulator may include an inductor selectively coupled to an output and a power supply. The regulator may also include a controller configured to detect an over-current event if an amount of current flowing from the power supply to the inductor is equal to or greater than a current threshold and detect a low-voltage event if a voltage at the output is less than or equal to a reference voltage. Further, in response to the over-current event and the low-voltage event, the controller may be configured to prevent current from flowing from the power supply to the inductor until substantially all energy stored by the inductor has been dissipated.

    Abstract translation: 示例性实施例涉及降压调节器。 降压调节器可以包括选择性地耦合到输出端和电源的电感器。 调节器还可以包括控制器，其被配置为如果从电源流向电感器的电流量等于或大于电流阈值，则检测过电流事件，并且如果输出端的电压检测到低电压事件 小于或等于参考电压。 此外，响应于过电流事件和低电压事件，控制器可以被配置为防止电流从电源流向电感器，直到电感器存储的基本上所有的能量已经消散为止。

    DUTY LOCKED LOOP CIRCUIT
    6.
    发明申请
    DUTY LOCKED LOOP CIRCUIT 有权

    公开(公告)号：US20190319610A1

    公开(公告)日：2019-10-17

    申请号：US15953157

    申请日：2018-04-13

    Applicant: Qualcomm Incorporated

    Inventor： Guolei YU ,  Ajay Kumar KOSARAJU ,  CHARLES TUTEN ,  Marko KOSKI ,  Aniruddha BASHAR

    IPC: H03K3/017

    Abstract: The present disclosure provides a duty locked loop circuit that includes a switch network including a first electronic switch device controlled by a first control signal that is based on a first input signal and a second electronic switch device controlled by a second control signal that is based on a second input signal. The duty locked loop circuit includes an integrator circuit electrically connected to the switch network. The integrator circuit is configured to generate an output voltage proportional to an integral of a difference between a first duty cycle of the first input signal and a second duty cycle of the second input signal. The duty locked loop circuit includes an output circuit configured to generate an output signal having an output duty cycle that is based on the output voltage.

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