公开(公告)号：US20170279352A1

公开(公告)日：2017-09-28

申请号：US15348923

申请日：2016-11-10

Applicant: QUALCOMM Incorporated

Inventor： Ajay Kumar KOSARAJU ,  Guolei YU ,  Yi-Cheng WAN ,  Sugato MUKHERJEE

IPC: H02M3/157 ,  G01R19/165 ,  H02M1/08

CPC classification number: H02M3/157 ,  G01R19/16571 ,  H02M1/08 ,  H02M3/1563 ,  H02M2001/0009 ,  H02M2001/0032 ,  Y02B70/16

Abstract: A duty cycle estimation circuit includes a latch circuit that receives a clock signal for a voltage regulator. The latch circuit outputs a duty cycle estimate. The duty cycle estimation circuit also includes a low pass filter coupled to an output of the latch circuit to receive the duty cycle estimate. The duty cycle estimation circuit further includes a comparator that receives, as input, an output of the low pass filter and a voltage regulator output. The comparator feeds back a feedback signal to the latch circuit.

公开(公告)号：US20190319610A1

公开(公告)日：2019-10-17

申请号：US15953157

申请日：2018-04-13

Applicant: Qualcomm Incorporated

Inventor： Guolei YU ,  Ajay Kumar KOSARAJU ,  CHARLES TUTEN ,  Marko KOSKI ,  Aniruddha BASHAR

IPC: H03K3/017

Abstract: The present disclosure provides a duty locked loop circuit that includes a switch network including a first electronic switch device controlled by a first control signal that is based on a first input signal and a second electronic switch device controlled by a second control signal that is based on a second input signal. The duty locked loop circuit includes an integrator circuit electrically connected to the switch network. The integrator circuit is configured to generate an output voltage proportional to an integral of a difference between a first duty cycle of the first input signal and a second duty cycle of the second input signal. The duty locked loop circuit includes an output circuit configured to generate an output signal having an output duty cycle that is based on the output voltage.