公开(公告)号：US12020746B2

公开(公告)日：2024-06-25

申请号：US17675993

申请日：2022-02-18

Applicant: QUALCOMM Incorporated

Inventor： Rejeesh Ammanath Vijayan ,  Rahul Sahu ,  Pradeep Raj

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: A memory with reduced power consumption during a write assist period is provided that includes a series of inverters configured to delay a write assist signal to form a delayed write assist signal at a first terminal of a boost capacitor. A cutoff switch transistor couples between ground and a ground node of a final inverter in the series of inverters. A clock circuit switches off the cutoff switch transistor to isolate the first terminal of the boost capacitor before an end of a write assist period.

公开(公告)号：US20230267993A1

公开(公告)日：2023-08-24

申请号：US17675993

申请日：2022-02-18

Applicant: QUALCOMM Incorporated

Inventor： Rejeesh Ammanath Vijayan ,  Rahul Sahu ,  Pradeep Raj

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: A memory with reduced power consumption during a write assist period is provided that includes a series of inverters configured to delay a write assist signal to form a delayed write assist signal at a first terminal of a boost capacitor. A cutoff switch transistor couples between ground and a ground node of a final inverter in the series of inverters. A clock circuit switches off the cutoff switch transistor to isolate the first terminal of the boost capacitor before an end of a write assist period.