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    High-speed multi-port memory supporting collision
    1.
    发明授权
    High-speed multi-port memory supporting collision 有权

    公开(公告)号：US12183393B2

    公开(公告)日：2024-12-31

    申请号：US18603118

    申请日：2024-03-12

    Applicant: QUALCOMM Incorporated

    Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta

    IPC: G11C11/418 ,  G11C11/419

    Abstract: A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.

    Memory Write Assist with Reduced Switching Power
    2.
    发明公开
    Memory Write Assist with Reduced Switching Power 审中-公开

    公开(公告)号：US20230267993A1

    公开(公告)日：2023-08-24

    申请号：US17675993

    申请日：2022-02-18

    Applicant: QUALCOMM Incorporated

    Inventor： Rejeesh Ammanath Vijayan ,  Rahul Sahu ,  Pradeep Raj

    IPC: G11C11/419

    CPC classification number: G11C11/419

    Abstract: A memory with reduced power consumption during a write assist period is provided that includes a series of inverters configured to delay a write assist signal to form a delayed write assist signal at a first terminal of a boost capacitor. A cutoff switch transistor couples between ground and a ground node of a final inverter in the series of inverters. A clock circuit switches off the cutoff switch transistor to isolate the first terminal of the boost capacitor before an end of a write assist period.

    Architecture to improve write-ability in SRAM
    3.
    发明授权
    Architecture to improve write-ability in SRAM 有权

    公开(公告)号：US09721650B1

    公开(公告)日：2017-08-01

    申请号：US15269620

    申请日：2016-09-19

    Applicant: QUALCOMM Incorporated

    Inventor： Pradeep Raj ,  Sharad Kumar Gupta ,  Rahul Sahu ,  Lakshmikantha Holla Vakwadi

    IPC: G11C11/412 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C5/025 ,  G11C5/14

    Abstract: A memory and apparatus are disclosed. The memory includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core. Additionally, the memory includes a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core. The apparatus includes at least one processor. The apparatus also includes a memory array. The memory array includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core and a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core.

    Access assist with wordline adjustment with tracking cell
    5.
    发明授权
    Access assist with wordline adjustment with tracking cell 有权

    公开(公告)号：US10811088B2

    公开(公告)日：2020-10-20

    申请号：US16299413

    申请日：2019-03-12

    Applicant: QUALCOMM Incorporated

    Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta

    IPC: G11C11/419 ,  G11C16/04 ,  G11C16/12 ,  G11C16/08

    Abstract: Methods and apparatuses to adjust wordline voltage level are presented. An apparatus includes multiple memory cells arranged in multiple rows. A wordline is configured to couple to one row of the multiple rows for a read or write operation. A wordline driving circuit is configured to provide a voltage level to the wordline to facilitate the read or write operation. A tracking circuit is configured to emulate a characteristic of one of the multiple memory cells. A pull-down circuit is configured to lower the voltage level of the wordline by an amount, based on the tracking circuit, to access the one row of the multiple rows in the read or write operation. A method includes emulating a characteristic of one of multiple of memory cells and lowering a voltage level of the wordline by an amount to access one row of the multiple rows in the read or write operation.

    ACCESS ASSIST WITH WORDLINE ADJUSTMENT WITH TRACKING CELL
    6.
    发明申请
    ACCESS ASSIST WITH WORDLINE ADJUSTMENT WITH TRACKING CELL 审中-公开

    公开(公告)号：US20200294580A1

    公开(公告)日：2020-09-17

    申请号：US16299413

    申请日：2019-03-12

    Applicant: QUALCOMM Incorporated

    Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta

    IPC: G11C11/419 ,  G11C16/08 ,  G11C16/12 ,  G11C16/04

    Abstract: Methods and apparatuses to adjust wordline voltage level are presented. An apparatus includes multiple memory cells arranged in multiple rows. A wordline is configured to couple to one row of the multiple rows for a read or write operation. A wordline driving circuit is configured to provide a voltage level to the wordline to facilitate the read or write operation. A tracking circuit is configured to emulate a characteristic of one of the multiple memory cells. A pull-down circuit is configured to lower the voltage level of the wordline by an amount, based on the tracking circuit, to access the one row of the multiple rows in the read or write operation. A method includes emulating a characteristic of one of multiple of memory cells and lowering a voltage level of the wordline by an amount to access one row of the multiple rows in the read or write operation.

    Memory write assist with reduced switching power
    10.
    发明授权
    Memory write assist with reduced switching power 有权

    公开(公告)号：US12020746B2

    公开(公告)日：2024-06-25

    申请号：US17675993

    申请日：2022-02-18

    Applicant: QUALCOMM Incorporated

    Inventor： Rejeesh Ammanath Vijayan ,  Rahul Sahu ,  Pradeep Raj

    IPC: G11C11/419

    CPC classification number: G11C11/419

    Abstract: A memory with reduced power consumption during a write assist period is provided that includes a series of inverters configured to delay a write assist signal to form a delayed write assist signal at a first terminal of a boost capacitor. A cutoff switch transistor couples between ground and a ground node of a final inverter in the series of inverters. A clock circuit switches off the cutoff switch transistor to isolate the first terminal of the boost capacitor before an end of a write assist period.

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