公开(公告)号：US20210073650A1

公开(公告)日：2021-03-11

申请号：US17016130

申请日：2020-09-09

Applicant: QUALCOMM Incorporated

Inventor： Matthias REISSER ,  Saurabh Kedar PITRE ,  Xiaochun ZHU ,  Edward Harris TEAGUE ,  Zhongze WANG ,  Max WELLING

IPC: G06N3/10 ,  G06N3/04 ,  G06F17/16

Abstract: In one embodiment, a method of simulating an operation of an artificial neural network on a binary neural network processor includes receiving a binary input vector for a layer including a probabilistic binary weight matrix and performing vector-matrix multiplication of the input vector with the probabilistic binary weight matrix, wherein the multiplication results are modified by simulated binary-neural-processing hardware noise, to generate a binary output vector, where the simulation is performed in the forward pass of a training algorithm for a neural network model for the binary-neural-processing hardware.

公开(公告)号：US20230376851A1

公开(公告)日：2023-11-23

申请号：US18319259

申请日：2023-05-17

Applicant: QUALCOMM Incorporated

Inventor： Mingu LEE ,  Saurabh Kedar PITRE ,  Tianyu JIANG ,  Christopher LOTT

IPC: G06N20/00

CPC classification number: G06N20/00

Abstract: Certain aspects of the present disclosure provide techniques and apparatus for performing machine learning. In one example, an input data sequence is accessed, and the input data sequence is sliced based on a slice length hyperparameter to generate a stacked slice input data representation. The stacked slice input data representation is processed with a slice attention layer to generate a stacked slice output data representation. The stacked slice output data representation is de-sliced to generate an output data sequence.