公开(公告)号：US20230025068A1

公开(公告)日：2023-01-26

申请号：US17813834

申请日：2022-07-20

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Zhongze WANG ,  Titash RAKSHIT

IPC: G06N3/063 ,  G06N3/04 ,  G06F15/80

Abstract: Methods and apparatus for performing machine learning tasks, and in particular, a hybrid architecture that includes both neural processing unit (NPU) and compute-in-memory (CIM) elements. One example neural-network-processing circuit generally includes a plurality of CIM processing elements (PEs), a plurality of neural processing unit (NPU) PEs, and a bus coupled to the plurality of CIM PEs and to the plurality of NPU PEs. One example method for neural network processing generally includes processing data in a neural-network-processing circuit comprising a plurality of CIM PEs, a plurality of NPU PEs, and a bus coupled to the plurality of CIM PEs and to the plurality of NPU PEs; and transferring the processed data between at least one of the plurality of CIM PEs and at least one of the plurality of NPU PEs via the bus.

公开(公告)号：US20220230679A1

公开(公告)日：2022-07-21

申请号：US17152564

申请日：2021-01-19

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash MIRHAJ ,  Xiaonan CHEN ,  Ankit SRIVASTAVA ,  Sameer WADHWA ,  Zhongze WANG

IPC: G11C11/419 ,  G06F7/544

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line. A write driver controls a power supply voltage to the cross-coupled inverters, the first switch, and the second switch to capacitively write the stored bit to the pair of cross-coupled inverters.

公开(公告)号：US20210240447A1

公开(公告)日：2021-08-05

申请号：US16778749

申请日：2020-01-31

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Zhongze WANG ,  Periannan CHIDAMBARAM

IPC: G06F7/68 ,  G06F7/533

Abstract: Certain aspects provide methods and apparatus for multiplication of digital signals. In accordance with certain aspects, a multiplication circuit may be used to multiply a portion of a first digital input signal with a portion of a second digital input signal via a first multiplier circuit to generate a first multiplication signal, and multiply another portion of the first digital input signal with another portion of the second digital input signal via a second multiplier circuit to generate a second multiplication signal. A third multiplier circuit and multiple adder circuits may be used to generate an output of the multiplication circuit based on the first and second multiplication signals.

公开(公告)号：US20210133549A1

公开(公告)日：2021-05-06

申请号：US16669855

申请日：2019-10-31

Applicant: QUALCOMM Incorporated

Inventor： Zhongze WANG ,  Xia LI ,  Xiaochun ZHU

IPC: G06N3/063 ,  G11C11/412 ,  G11C11/419

Abstract: Certain aspects provide a circuit for in-memory computation. The circuit generally includes a first memory cell, and a first computation circuit. The first computation circuit may include a first switch having a control input coupled to an output of the first memory cell, a second switch coupled between a node of the first computation circuit and the first switch, a control input of the second switch being coupled to a discharge word-line (DCWL), a capacitive element coupled between the node and a reference potential node, a third switch coupled between the node and a read bit-line (RBL), and a fourth switch coupled between the node and an activation (ACT) line.

公开(公告)号：US20160071795A1

公开(公告)日：2016-03-10

申请号：US14483110

申请日：2014-09-10

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Stanley Seungchul SONG ,  Kern RIM ,  Zhongze WANG ,  Jeffrey Junhao XU

IPC: H01L23/522 ,  H01L49/02 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/8234 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/823475 ,  H01L27/0805 ,  H01L28/60 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device capacitor structure within middle of line (MOL) layers includes a first MOL interconnect layer. The first MOL interconnect layer may include active contacts between a set of dummy gate contacts on an active surface of a semiconductor substrate. The device capacitor structure also includes a second MOL interconnect layer. The second MOL interconnect layer may include a set of stacked contacts directly on exposed ones of the active contacts. The second MOL interconnect layer may also include a set of fly-over contacts on portions of an etch-stop layer on some of the active contacts. The fly-over contacts and the stacked contacts may provide terminals of a set of device capacitors.

Abstract translation: 线路（MOL）层中间的器件电容器结构包括第一MOL互连层。 第一MOL互连层可以包括半导体衬底的有源表面上的一组虚拟栅极触点之间的有源触点。 器件电容器结构还包括第二MOL互连层。 第二MOL互连层可以直接在活动触点的暴露的一个上包括一组堆叠的触点。 第二MOL互连层还可以包括在一些有源触点上的蚀刻停止层的部分上的一组飞越触点。 飞越触点和堆叠的触点可以提供一组器件电容器的端子。

公开(公告)号：US20160005822A1

公开(公告)日：2016-01-07

申请号：US14321568

申请日：2014-07-01

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Choh Fei YEAP ,  Kern RIM ,  Zhongze WANG

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/41783 ,  H01L29/7834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods are directed to a three-terminal semiconductor device including a self-aligned via for connecting to a gate terminal Hardmasks and spacers formed over top portions and sidewall portions of a drain connection to a drain terminal and a source connection to a source terminal protect and insulate the drain connection and the source connection, such that short circuits are avoided between the source and drain connections and the self-aligned via. The self-aligned via provides a direct metal-gate connection path between the gate terminal and a metal line such as a M1 metal line while avoiding a separate gate connection layer.

Abstract translation: 系统和方法涉及三端子半导体器件，其包括用于连接到栅极端子的自对准通孔。硬掩模和形成在到漏极端子的漏极连接的顶部和侧壁部分上的间隔物以及到源极端子的源极连接 保护和绝缘漏极连接和源极连接，从而避免在源极和漏极连接和自对准通孔之间产生短路。 自对准通孔在栅极端子和诸如M1金属线的金属线之间提供直接的金属栅极连接路径，同时避免了单独的栅极连接层。

公开(公告)号：US20150235948A1

公开(公告)日：2015-08-20

申请号：US14274184

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Zhongze WANG ,  Ohsang KWON ,  Kern RIM ,  John Jianhong ZHU ,  Xiangdong CHEN ,  Foua VANG ,  Raymond George STEPHANY ,  Choh Fei YEAP

IPC: H01L23/528 ,  H01L27/088 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/42312 ,  H01L2027/11866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate.

Abstract translation: 半导体器件包括栅极和邻近栅极的第一有源触点。 这种器件还包括电耦合到第一有源触点的第一堆叠触点，包括在侧壁上电隔离第一堆叠触头与栅极的第一隔离层。 该装置还包括电连接到门的第一通孔和第一堆叠接触件上的着陆。 第一通孔将第一堆叠触点和第一有源触点电耦合到栅极以将栅极接地。

公开(公告)号：US20230065725A1

公开(公告)日：2023-03-02

申请号：US17465550

申请日：2021-09-02

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Zhongze WANG ,  Francois Ibrahim ATALLAH

IPC: G06N3/08 ,  G06F7/544 ,  G06N3/063 ,  G06N3/04

Abstract: Methods and apparatus for performing machine learning tasks, and in particular, to a neural-network-processing architecture and circuits for improved performance through depth parallelism. One example neural-network-processing circuit generally includes a plurality of groups of processing element (PE) circuits, wherein each group of PE circuits comprises a plurality of PE circuits configured to process in parallel an input at a plurality of depths.

公开(公告)号：US20230047364A1

公开(公告)日：2023-02-16

申请号：US17398791

申请日：2021-08-10

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Zhongze WANG

IPC: G06N3/08 ,  G06F7/523 ,  G06F7/50

Abstract: Methods and apparatus for performing machine learning tasks, and in particular, to a neural-network-processing architecture and circuits for improved handling of partial accumulation results in weight-stationary operations, such as operations occurring in compute-in-memory (CIM) processing elements (PEs). One example PE circuit for machine learning generally includes an accumulator circuit, a flip-flop array having an input coupled to an output of the accumulator circuit, a write register, and a first multiplexer having a first input coupled to an output of the write register, having a second input coupled to an output of the flip-flop array, and having an output coupled to a first input of the first accumulator circuit.

公开(公告)号：US20210073650A1

公开(公告)日：2021-03-11

申请号：US17016130

申请日：2020-09-09

Applicant: QUALCOMM Incorporated

Inventor： Matthias REISSER ,  Saurabh Kedar PITRE ,  Xiaochun ZHU ,  Edward Harris TEAGUE ,  Zhongze WANG ,  Max WELLING

IPC: G06N3/10 ,  G06N3/04 ,  G06F17/16

Abstract: In one embodiment, a method of simulating an operation of an artificial neural network on a binary neural network processor includes receiving a binary input vector for a layer including a probabilistic binary weight matrix and performing vector-matrix multiplication of the input vector with the probabilistic binary weight matrix, wherein the multiplication results are modified by simulated binary-neural-processing hardware noise, to generate a binary output vector, where the simulation is performed in the forward pass of a training algorithm for a neural network model for the binary-neural-processing hardware.