公开(公告)号：US09311596B2

公开(公告)日：2016-04-12

申请号：US14198550

申请日：2014-03-05

Applicant: QUALCOMM TECHNOLOGIES INC.

Inventor： Eugene M. Izhikevich ,  Botond Szatmary ,  Csaba Petre ,  Filip Piekniewski ,  Michael-David Nakayoshi Canoy ,  Robert Howard Kimball ,  Jan Krzys Wegrzyn

IPC: G06N3/04 ,  G06N3/02 ,  G06N3/10

CPC classification number: G06N3/10 ,  G06N3/04 ,  G06N3/049

Abstract: A simple format is disclosed and referred to as Elementary Network Description (END). The format can fully describe a large-scale neuronal model and embodiments of software or hardware engines to simulate such a model efficiently. The architecture of such neuromorphic engines is optimal for high-performance parallel processing of spiking networks with spike-timing dependent plasticity. Methods for managing memory in a processing system are described whereby memory can be allocated among a plurality of elements and rules configured for each element such that the parallel execution of the spiking networks is most optimal.

Abstract translation: 公开了一种简单的格式，并被称为基本网络描述（END）。 该格式可以充分描述大规模神经元模型和软件或硬件引擎的实施例，以有效地模拟这种模型。 这种神经形态发动机的架构对于具有尖峰时间依赖可塑性的加标网络的高性能并行处理是最佳的。 描述了用于管理处理系统中的存储器的方法，其中可以在为每个元件配置的多个元件和规则之间分配存储器，使得加标网络的并行执行是最佳的。

公开(公告)号：US09165245B2

公开(公告)日：2015-10-20

申请号：US14275663

申请日：2014-05-12

Applicant: QUALCOMM TECHNOLOGIES INC.

Inventor： Eugene M. Izhikevich ,  Filip Piekniewski ,  Jayram Moorkanikara Nageswaran ,  Jeffrey Alexander Levin ,  Venkat Rangan ,  Erik Christopher Malone

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

CPC classification number: G06N3/049 ,  G06N3/063 ,  G06N3/08

Abstract: Apparatus and methods for partial evaluation of synaptic updates in neural networks. In one embodiment, a pre-synaptic unit is connected to a several post synaptic units via communication channels. Information related to a plurality of post-synaptic pulses generated by the post-synaptic units is stored by the network in response to a system event. Synaptic channel updates are performed by the network using the time intervals between a pre-synaptic pulse, which is being generated prior to the system event, and at least a portion of the plurality of the post synaptic pulses. The system event enables removal of the information related to the portion of the post-synaptic pulses from the storage device. A shared memory block within the storage device is used to store data related to post-synaptic pulses generated by different post-synaptic nodes. This configuration enables memory use optimization of post-synaptic units with different firing rates.

Abstract translation: 用于部分评估神经网络中突触更新的装置和方法。 在一个实施例中，突触前单元经由通信信道连接到几个后突触单元。 与由突触后单元产生的多个突触后脉冲相关的信息由网络响应于系统事件存储。 突触信道更新由网络使用在系统事件之前产生的预触觉脉冲与多个突触后脉冲的至少一部分之间的时间间隔来执行。 系统事件使得能够从存储设备去除与突触后部分脉冲相关的信息。 存储设备内的共享存储器块用于存储与由不同的突触后节点产生的突触后脉冲相关的数据。 这种配置使得具有不同发射速率的突触后单元的存储器使用优化成为可能。

公开(公告)号：US09092738B2

公开(公告)日：2015-07-28

申请号：US14198446

申请日：2014-03-05

Applicant: QUALCOMM TECHNOLOGIES INC.

Inventor： Eugene M. Izhikevich ,  Botond Szatmary ,  Csaba Petre ,  Filip Piekniewski ,  Jayram Moorkanikara Nageswaran

IPC: G06N3/10 ,  G06N3/08 ,  G05B13/02

CPC classification number: G06N3/08 ,  G05B13/027 ,  G06N3/049 ,  G06N3/10

Abstract: A simple format is disclosed and referred to as Elementary Network Description (END). The format can fully describe a large-scale neuronal model and embodiments of software or hardware engines to simulate such a model efficiently. The architecture of such neuromorphic engines is optimal for high-performance parallel processing of spiking networks with spike-timing dependent plasticity. The software and hardware engines are optimized to take into account short-term and long-term synaptic plasticity in the form of LTD, LTP, and STDP.

Abstract translation: 公开了一种简单的格式，并被称为基本网络描述（END）。 该格式可以充分描述大规模神经元模型和软件或硬件引擎的实施例，以有效地模拟这种模型。 这种神经形态发动机的架构对于具有尖峰时间依赖可塑性的加标网络的高性能并行处理是最佳的。 软件和硬件引擎经过优化考虑了LTD，LTP和STDP形式的短期和长期突触可塑性。