公开(公告)号：US11604505B2

公开(公告)日：2023-03-14

申请号：US17136175

申请日：2020-12-29

Applicant: QUALCOMM incorporated

Inventor： Bharat Kumar Rangarajan ,  Rajesh Arimilli ,  Rengarajan Ragavan

IPC: G06F1/3237 ,  G06F21/74 ,  G06F3/06 ,  G06F15/78

Abstract: Various embodiments include methods and devices for system on chip infrastructure of system on chip infrastructure secure memory access and power management. Some embodiments, include determining whether a processor is performing a secure memory access transaction, and gating a clock signal from being transmitted to a secure portion of a memory in response to determining that the processor is not performing a secure memory access transaction. Some embodiments include determining whether any processor is operating in a secure mode, and transmitting a retention signal to the secure portion of the memory in response to determining that no processor is operating in a secure mode. The retention signal may be configured to set a retention state for the secure portion of the memory.