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    Method and system for low power internetwork communication with machine devices
    1.
    发明申请
    Method and system for low power internetwork communication with machine devices 有权

    公开(公告)号：US20250004528A1

    公开(公告)日：2025-01-02

    申请号：US18732609

    申请日：2024-06-03

    Applicant: M2MD Technologies, Inc.

    Inventor： Charles M. Link, II

    IPC: G06F1/3209 ,  G06F1/3237 ,  G06F1/3246 ,  G06F1/3287 ,  H04W52/02

    Abstract: A wireless mobile device in a public communication network receives network-initiated signaling or messaging, while operating in a battery-conserving mode, or modes that, keep(s) minimal baseband processing functions awake. The baseband processing functions process incoming signaling or data in a received message to determine whether to act further on information in the incoming message by enabling additional processing capability in the mobile device. The mobile device may have permanent template criteria values, either coded in firmware or implemented in hardware, or temporary template criteria values, stored in RAM or processor registers, that are compared to values of an incoming message or datagram from the mobile network to determine whether to perform additional actions, such as awakening an application processor. Multiple templates may co-exist to allow different incoming datagrams to cause the device to take some additional action, respond, or even ignore information in an incoming datagram or message.

    SYSTEMS AND METHODS FOR CLOCK GATING
    2.
    发明申请
    SYSTEMS AND METHODS FOR CLOCK GATING 有权

    公开(公告)号：US20240411356A1

    公开(公告)日：2024-12-12

    申请号：US18744598

    申请日：2024-06-15

    Applicant: SiFive, Inc.

    Inventor： Edward McLellan ,  Arjun Pal Chowdury ,  Paul Walmsley

    IPC: G06F1/3237 ,  G06F1/3206

    Abstract: Described are systems and methods for clock gating components on a system-on-chip. A processing system includes one or more cores, each core including a clock gating enable bit register which is set by software when an expected idle period of the core meets or exceeds a clock gating threshold, and a power management unit connected to the one or more cores. The power management unit configured to receive an idle notification from a core of the one or more cores and initiate clock gating a clock associated with the core when the core and additional logic is quiescent and the clock gating enable bit register is set. The clock gating threshold is a defined magnitude greater than a clock wake-up time.

    DYNAMIC POWER REDUCTION TECHNIQUE FOR ULTRASOUND SYSTEMS
    3.
    发明公开
    DYNAMIC POWER REDUCTION TECHNIQUE FOR ULTRASOUND SYSTEMS 审中-公开

    公开(公告)号：US20240319778A1

    公开(公告)日：2024-09-26

    申请号：US18731840

    申请日：2024-06-03

    Applicant: FUJIFILM SONOSITE, INC.

    Inventor： Justin M. COUGHLIN ,  Mitchell S. KAPLAN ,  Michael R. HANSEN ,  William R. OGLE

    IPC: G06F1/3237 ,  G01S7/521 ,  G01S7/526 ,  G01S15/89 ,  G06F1/08

    CPC classification number: G06F1/3237 ,  G01S7/521 ,  G01S7/526 ,  G01S15/8906 ,  G06F1/08

    Abstract: Methods and apparatuses for dynamic power reduction in ultrasound systems are described. Subsystems including a first subsystem to be placed in a reduced power consumption state are determined. The first subsystem includes a receive path having a receiver to receive acoustic signals representing echoes. A control subsystem to control clocking of the receive path in response to at least one of a plurality of real-time signals is determined. The control subsystem is configured to provide one or more clocks to the receive path to turn on the receiver while valid echo signals are expected to arrive at the receiver At least one of the plurality of real-time signals indicates a state of imaging operations. The control subsystem is configured to provide one or more clocks to the receive path during a first mode based on the state of the imaging operations.

    Interface clock management
    7.
    发明授权
    Interface clock management 有权

    公开(公告)号：US11681648B2

    公开(公告)日：2023-06-20

    申请号：US17559975

    申请日：2021-12-22

    Applicant: Rambus Inc.

    Inventor： Yuanlong Wang

    IPC: G06F1/00 ,  G06F13/42 ,  G06F1/3237 ,  G06F1/3206 ,  G06F1/3234

    CPC classification number: G06F13/4243 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3275 ,  Y02B70/10 ,  Y02D10/00 ,  Y02D30/50

    Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

    Clock Frequency Adjustment For Semi-Conductor Devices
    8.
    发明申请
    Clock Frequency Adjustment For Semi-Conductor Devices 有权

    公开(公告)号：US20230048899A1

    公开(公告)日：2023-02-16

    申请号：US17977456

    申请日：2022-10-31

    Applicant: Imagination Technologies Limited

    Inventor： Paul Rowland

    IPC: H04L7/00 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324

    Abstract: A method and an apparatus for clocking data processing modules, with different average clock frequencies and for transferring data between the modules are provided. The apparatus includes a device for providing a common clock signal to the modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. The clock pulses are applied to the modules between which the data is to be transferred at times consistent with the data transfer.

    METHOD FOR MODELING POWER CONSUMPTION OF AN INTEGRATED CIRCUIT AND POWER CONSUMPTION MODELING SYSTEM PERFORMING THE SAME
    9.
    发明申请
    METHOD FOR MODELING POWER CONSUMPTION OF AN INTEGRATED CIRCUIT AND POWER CONSUMPTION MODELING SYSTEM PERFORMING THE SAME 有权

    公开(公告)号：US20230010159A1

    公开(公告)日：2023-01-12

    申请号：US17849707

    申请日：2022-06-27

    Applicant: Baum Design Systems Co., Ltd.

    Inventor： In Hak HAN ,  Jin Hyeong PARK

    IPC: G06F1/3237 ,  G06F30/327 ,  G06F30/396

    Abstract: Example embodiments relate to a method for modeling power consumption of an integrated circuit, the method may comprise, determining, by the processor, a hierarchy structure regarding a gating level according to a clock flow of a plurality of clock gating cells included in the integrated circuit, determining, by the processor, a first clock gating domain corresponding to a first clock gating cell and a second clock gating domain corresponding to a second clock gating cell located in a lower level of the hierarchy of the first clock gating cell based on the hierarchy structure, calculating, by the processor, power consumption of the second clock gating domain based on a first logic level of a first clock gating enable signal applied to the first clock gating cell, and modeling, by the processor, power consumption of the integrated circuit based on the power consumption of the second clock gating domain.

    Interrupt controller and method of managing an interrupt controller
    10.
    发明授权
    Interrupt controller and method of managing an interrupt controller 有权

    公开(公告)号：US11550744B2

    公开(公告)日：2023-01-10

    申请号：US17229307

    申请日：2021-04-13

    Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

    Inventor： Jawad Benhammadi ,  Sylvain Meyer

    IPC: G06F13/24 ,  G06F13/16 ,  G06F21/85 ,  H03K19/20 ,  G06F1/3237

    Abstract: In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.

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