公开(公告)号：US20240356842A1

公开(公告)日：2024-10-24

申请号：US18302150

申请日：2023-04-18

Applicant: Quanta Computer Inc.

Inventor： Chun-Ching YU ,  Ching-Chuan LIU ,  Hsi-Han LIN ,  Shuen-Hung WANG

IPC: H04L45/00

CPC classification number: H04L45/70

Abstract: A computing system including two or more controllers, a universal asynchronous receiver-transmitter (UART) multiplexer, and a combinational logic circuit is provided. The two of more controllers include a first controller and a second controller. The first controller is configured to provide a first status signal and a first select control signal, and the second controller is configured to provide a second status signal and a second select control signal. The UART multiplexer is configured to provide UART output from at least a first UART input and a second UART input based on a UART select signal. The combinational logic circuit is configured to determine the UART select signal is one of the first select control signal or the second select control signal based at least in part on the first status signal and the second status signal.