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公开(公告)号：US20190249678A1
公开(公告)日：2019-08-15
申请号：US15895360
申请日：2018-02-13
Applicant: QUANTA COMPUTER INC.
Inventor： Chun-Ching YU , Shuen-Hung WANG
Abstract: The present disclosure provides a system and method for controlling a plurality of cooling fan modules using a management controller and a multiplex switch. The multiplex switch connects the management controller to the plurality of cooling fan modules. The multiplex switch can enable the management controller to select a specific cooling fan module from the plurality of cooling fan modules. Once the specific cooling fan module is selected, the multiplex switch can connect to the specific cooling fan module, enable the management controller to monitor operating characteristics of the specific cooling fan module, and control power or current being delivered to the specific cooling fan module.
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公开(公告)号：US20190235965A1
公开(公告)日：2019-08-01
申请号：US15985349
申请日：2018-05-21
Applicant: QUANTA COMPUTER INC.
Inventor： Chi-Han PENG , Chun-Ching YU , Shuen-Hung WANG
CPC classification number: G06F11/1456 , G06F1/30 , G06F1/3225 , G06F11/1441 , G06F11/1448 , G06F12/0868
Abstract: Systems and methods are provided for preserving data in memory modules of a computer system. An exemplary method can detect that a software preservation process is needed for a computer system, and thereafter performs the software preservation process. The software preservation process can begin by detecting the initiation of a reduced power mode in a computer system. A syncing process of data contents can then be initiated in a processing unit of the computer system. Next, the computer system can automatically save data contents of a memory module. The software preservation process is completed by turning off a power supply unit of the computer system.
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公开(公告)号：US20190053405A1
公开(公告)日：2019-02-14
申请号：US15673031
申请日：2017-08-09
Applicant: QUANTA COMPUTER INC.
Inventor： Shuen-Hung WANG , Ting-Chen KO
Abstract: Various examples of the present disclosure provide a multi-node fan control switch and systems and methods for controlling one or more cooling fans of a node using a fan control switch and a specific controller (e.g., BMC or a specific processor) of the node. The node also includes a watch dog circuit. The watch dog circuit can monitor health of the specific controller and, in response to determining that the specific controller has failed, enable the fan control switch to an external mode to allow a controller of a neighboring node in the rack system to control the one or more cooling fans of the node.
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公开(公告)号：US20200285455A1
公开(公告)日：2020-09-10
申请号：US16294566
申请日：2019-03-06
Applicant: QUANTA COMPUTER INC.
Inventor： Kai-Yeh PAN , Chun-Ching YU , Shuen-Hung WANG
Abstract: A multiple storage node system including a first and second node is provided. The first node includes a first baseboard management controller (BMC), a first flash ROM configured to store a first flash image, and a first switch device configured to connect the first BMC to the first flash ROM. The second node includes an exact configuration of the first node. The first BMC is connected to the second switch device, and the second flash image is the same as the first flash.
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Patent Agency Ranking
公开(公告)号：US20160353603A1
公开(公告)日：2016-12-01
申请号：US14724989
申请日：2015-05-29
Applicant: Quanta Computer Inc.
Inventor： Maw-Zan JAU , Chih-Da WU , Shuen-Hung WANG
IPC: H05K7/14
CPC classification number: H05K7/1491
Abstract: A system includes a rear panel of a housing that includes a first compartment and a second compartment. The system further includes a first module of a first type coupled to the first compartment and a second module of a second type coupled to the second compartment. The first compartment is configured to couple to modules of the first type and the second type, and the second compartment is configured to couple to modules of the first type and the second type.
Abstract translation: 一种系统包括壳体的后面板，其包括第一隔室和第二隔室。 该系统还包括耦合到第一隔室的第一类型的第一模块和耦合到第二隔间的第二类型的第二模块。 第一隔室被配置为耦合到第一类型和第二类型的模块，并且第二隔间被配置为耦合到第一类型和第二类型的模块。
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公开(公告)号：US20240385610A1
公开(公告)日：2024-11-21
申请号：US18319676
申请日：2023-05-18
Applicant: Quanta Computer Inc.
Inventor： Le-Sheng CHOU , Sz-Chin SHIH , Shuen-Hung WANG , Hsien-Chang LI
IPC: G05B23/02
Abstract: A computing system includes one or more electronic components, a first programmable device, and a baseboard management controller (BMC). The first programmable device is communicatively coupled to a first subset of the one or more electronic components. The first programmable device is configured to detect event activities associated with the first subset and to store the event activities as stored first event data. The BMC includes a system event log. The BMC is communicatively coupled to the first programmable device. The BMC is configured to receive the stored first event data and to write the stored first event data in the system event log.
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公开(公告)号：US20240356842A1
公开(公告)日：2024-10-24
申请号：US18302150
申请日：2023-04-18
Applicant: Quanta Computer Inc.
Inventor： Chun-Ching YU , Ching-Chuan LIU , Hsi-Han LIN , Shuen-Hung WANG
IPC: H04L45/00
CPC classification number: H04L45/70
Abstract: A computing system including two or more controllers, a universal asynchronous receiver-transmitter (UART) multiplexer, and a combinational logic circuit is provided. The two of more controllers include a first controller and a second controller. The first controller is configured to provide a first status signal and a first select control signal, and the second controller is configured to provide a second status signal and a second select control signal. The UART multiplexer is configured to provide UART output from at least a first UART input and a second UART input based on a UART select signal. The combinational logic circuit is configured to determine the UART select signal is one of the first select control signal or the second select control signal based at least in part on the first status signal and the second status signal.
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公开(公告)号：US20170329736A1
公开(公告)日：2017-11-16
申请号：US15153014
申请日：2016-05-12
Applicant: Quanta Computer Inc.
Inventor： Chun-Chin YU , Shuen-Hung WANG
CPC classification number: G06F13/4068 , G06F3/0604 , G06F3/0653 , G06F3/0683 , G06F11/2092 , G06F13/1668 , G06F13/387 , G06F13/4282
Abstract: In some embodiments, a system for flexible non-volatile memory express drive management can include a first controller including a first drive register and a second drive register, a first processor communicatively coupled with the first drive register via a first serial bus, and a second processor communicatively coupled with the second drive register via a second serial bus. The system can also include a first set of non-volatile memory express drives communicatively coupled with the first processor via the first drive register, and a second set of non-volatile memory express drives communicatively coupled with the second processor via the second drive register and the second serial bus.
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公开(公告)号：US20170322899A1
公开(公告)日：2017-11-09
申请号：US15149032
申请日：2016-05-06
Applicant: Quanta Computer Inc.
Inventor： Hsiao-Tsu NI , Shuen-Hung WANG , Chia-Ju LEE
CPC classification number: G06F13/4022 , G06F12/0246 , G06F13/4282 , G06F2212/7202
Abstract: A system and method for dynamic reconfiguration of at least one peripheral bus switch of a system includes a management controller that detects whether a server system is connected to each peripheral bus slot of the system. The management controller selects a peripheral bus switch topology for the at least one peripheral bus switch, based on the detecting. The management controller sets each port of the at least one peripheral bus switch to either an upstream port configuration or a downstream port configuration, based on the peripheral bus switch topology.
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