公开(公告)号：US20170206168A1

公开(公告)日：2017-07-20

申请号：US15393232

申请日：2016-12-28

Applicant: RAMBUS INC.

Inventor： Trung DIEP ,  Hongzhong ZHENG

IPC: G06F12/1009 ,  G06F12/0811

CPC classification number: G06F12/1009 ,  G06F12/0811 ,  G06F12/0864 ,  G06F2212/283 ,  G06F2212/656 ,  G11C7/1072

Abstract: A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.