Memory component with adjustable core-to-interface data rate ratio

    公开(公告)号:US12094565B2

    公开(公告)日:2024-09-17

    申请号:US17301089

    申请日:2021-03-24

    Applicant: Rambus Inc.

    CPC classification number: G11C7/1066 G11C7/10 G11C7/1072

    Abstract: A memory component includes a memory bank comprising a plurality of storage cells and a data interface block configured to transfer data between the memory component and a component external to the memory component. The memory component further includes a plurality of column interface buses coupled between the memory bank and the data interface block, wherein a first column interface bus of the plurality of column interface buses is configured to transfer data between a first storage cell of the plurality of storage cells and the data interface block during a first access operation and wherein a second column interface bus of the plurality of column interface buses is configured to transfer the data between the first storage cell and the data interface block during a second access operation.

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