公开(公告)号：US20230113513A1

公开(公告)日：2023-04-13

申请号：US17886024

申请日：2022-08-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsunori TSUNETSUGU ,  Yasutaka NAKASHIBA

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/495 ,  H01L23/528

Abstract: A multilayer wiring structure in which a plurality of conductive films and a plurality of interlayer dielectric films are laminated is formed so as to cover a main surface of a first semiconductor chip. The conductive films include conductive films to which a low voltage is applied and conductive films to which a high voltage is applied. The conductive films to which the low voltage is applied are located below the conductive films to which the high voltage is applied and closer to the main surface of a semiconductor substrate. The conductive films are arranged as conductive films of at least one layer between a first inductor to which the low voltage is applied and a second inductor to which the high voltage is applied.