公开(公告)号：US20230411200A1

公开(公告)日：2023-12-21

申请号：US18191505

申请日：2023-03-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tsuyoshi KANAO ,  Koji OGATA

IPC: H01L21/683 ,  H01L21/66 ,  H01L21/304

CPC classification number: H01L21/6836 ,  H01L22/12 ,  H01L21/304 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: A method of manufacturing a semiconductor device includes: a grind step of forming a small thickness portion and a large thickness portion surrounding the small thickness portion in plan view by grinding a back surface of a semiconductor wafer; a preparation step of preparing a wafer holding member including a wafer placement surface and a back surface opposite to the wafer placement surface and having a larger thickness than a difference between a thickness of the large thickness portion and a thickness of the small thickness portion; and a placement step of placing the semiconductor wafer on the wafer holding member so that the small thickness portion of the semiconductor wafer and the wafer placement surface of the wafer holding member are in contact with each other on the back surface side of the semiconductor wafer.