公开(公告)号：US07451378B2

公开(公告)日：2008-11-11

申请号：US11623617

申请日：2007-01-16

申请人： Rajugopal Gubbi ,  Javaji Sunil Babu ,  Ramanujan K Valmiki

发明人： Rajugopal Gubbi ,  Javaji Sunil Babu ,  Ramanujan K Valmiki

IPC分类号： H03M13/00

CPC分类号： H03M13/2785 ,  H03M13/1515 ,  H03M13/2707 ,  H03M13/6356 ,  H03M13/6362

摘要： Systems and methods are provided for processing Multi-Protocol Encapsulation (MPE) under the DVB-H standard. The system includes: (a) a receive buffer having entries organized as columns and rows, the addresses for the entries in the receive buffer being arranged sequentially in column-major order; (b) a first process writing MPE data into the receive buffer, in the manner such that, for each frame, the application data portion and the error correction code portion are written sequentially in column major order, (c) a second process decoding the error correction code portion of each frame and which corrects the application data portion in accordance with the decoding; and (d) a third process reading out the application data portion from the receiver buffer column by column, the third process re-reading any column of the application portion that is corrected by the second process, when that column has previously been read by the third process.

摘要翻译： 提供了用于处理DVB-H标准下的多协议封装（MPE）的系统和方法。 该系统包括：（a）具有组织为列和行的条目的接收缓冲器，接收缓冲器中的条目的地址按列主要顺序排列; （b）将MPE数据写入接收缓冲器的第一过程，以对于每个帧的方式，应用数据部分和纠错码部分以列主要顺序被顺序地写入，（c）第二处理解码 每个帧的纠错码部分，并根据解码校正应用数据部分; 和（d）第三进程逐列从接收器缓冲器读出应用数据部分，第三进程重新读取由第二进程校正的应用部分的任何列，当该列先前被 第三个过程。

公开(公告)号：US07926046B2

公开(公告)日：2011-04-12

申请号：US11482579

申请日：2006-07-07

申请人： Soorgoli Ashok Halambi ,  Sarang Ramchandra Shelke ,  Bhramar Bhushan Vatsa ,  Dibyapran Sanyal ,  Nishant Manohar Nakate ,  Ramanujan K Valmiki ,  Sai Pramod Kumar Atmakuru ,  William C Salefski ,  Vidya Praveen

发明人： Soorgoli Ashok Halambi ,  Sarang Ramchandra Shelke ,  Bhramar Bhushan Vatsa ,  Dibyapran Sanyal ,  Nishant Manohar Nakate ,  Ramanujan K Valmiki ,  Sai Pramod Kumar Atmakuru ,  William C Salefski ,  Vidya Praveen

IPC分类号： G06F9/44 ,  G06F9/45

CPC分类号： G06F8/4452

摘要： This invention describes a compilation method of extracting and implementing an accelerator control program from an application source code in a processor based system. The application source code comprises arrays and loops. The input application source code is sequential, with loop, branch and call control structures, while the generated output of this invention has parallel execution semantics. The compilation method comprises the step of performing loop nest analysis, transformations and backend processes. The step of loop nest analysis consists of dependence analysis and pointer analysis. Dependence analysis determines the conflicts between the various references to arrays in the loop, and pointer analysis determines if two pointer references in a loop are in conflict. Transformations convert the loops from their original sequential execution semantics to parallel execution semantics. The back-end process determines the parameters and memory map of the accelerator and the hardware dependent software.

摘要翻译： 本发明描述了一种从基于处理器的系统中的应用源代码提取和实现加速器控制程序的编译方法。 应用程序源代码包括数组和循环。 输入应用源代码是循环，分支和调用控制结构的顺序，而本发明的生成输出具有并行执行语义。 编译方法包括执行循环嵌套分析，转换和后端处理的步骤。 循环嵌套分析的步骤包括依赖分析和指针分析。 依赖性分析确定循环中对数组的各种引用之间的冲突，指针分析确定循环中的两个指针引用是否相冲突。 转换将循环从原始的顺序执行语义转换为并行执行语义。 后端进程确定加速器和硬件相关软件的参数和存储器映射。

公开(公告)号：US07444442B2

公开(公告)日：2008-10-28

申请号：US11483018

申请日：2006-07-07

申请人： Shashank Dabral ,  Ramanujan K Valmiki

发明人： Shashank Dabral ,  Ramanujan K Valmiki

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： A method of reducing data transfer overheads in a 32-bit bus interface unit direct memory access architecture. The method comprises the steps of identifying the optimal number of data elements, that can be accessed as a single full-word transfer, setting data packing criteria and analysing the data pattern and determining the impact of offset direction on data packing. If the packing criteria are met, the data is compacted and fetched in four bytes or two half-words in one transaction by performing a full-word transfer instead of a partial transfer. If the packing criteria are not met, a single byte or a single half word is fetched. This invention provides a system for reducing data transfer overheads. The system comprises of an external address generation unit for generating external memory addresses and corresponding byte enables and a read local address generation unit for generating internal memory addresses and corresponding byte enables.

摘要翻译： 一种降低32位总线接口单元直接存储器访问架构中数据传输开销的方法。 该方法包括以下步骤：识别可作为单个全字传输访问的数据元素的最佳数量，设置数据打包标准并分析数据模式并确定偏移方向对数据打包的影响。 如果满足包装标准，则通过执行全字传输而不是部分传送，在一个事务中数据被压缩并以四字节或两个半字取出。 如果不满足打包标准，则取一个字节或单个半字。 本发明提供了一种用于减少数据传输开销的系统。 该系统包括用于产生外部存储器地址和相应字节使能的外部地址生成单元和用于产生内部存储器地址和对应字节使能的读取本地地址生成单元。