-
1.发明申请公开(公告)号：US20180054330A1
公开(公告)日：2018-02-22
申请号：US15677421
申请日：2017-08-15
Applicant: Rambus Inc.
Inventor： Chintan S. Thakkar , Kun-Yung Chang , Ting Wu
CPC classification number: H04L25/03057 , H04L7/0045 , H04L7/0058 , H04L7/0087 , H04L25/03063 , H04L2025/03369
Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.
-
公开(公告)号：US20150103875A1
公开(公告)日：2015-04-16
申请号：US14572590
申请日：2014-12-16
Applicant: Rambus Inc.
Inventor： Chintan S. Thakkar , Kun-Yung Chang , Ting Wu
CPC classification number: H04L25/03057 , H04L7/0045 , H04L7/0058 , H04L7/0087 , H04L25/03063 , H04L2025/03369
Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.
-
公开(公告)号：US09768986B2
公开(公告)日：2017-09-19
申请号：US15209375
申请日：2016-07-13
Applicant: Rambus Inc.
Inventor： Chintan S. Thakkar , Kun-Yung Chang , Ting Wu
CPC classification number: H04L25/03057 , H04L7/0045 , H04L7/0058 , H04L7/0087 , H04L25/03063 , H04L2025/03369
Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.
-
公开(公告)号：US20170070369A1
公开(公告)日：2017-03-09
申请号：US15209375
申请日：2016-07-13
Applicant: Rambus Inc.
Inventor： Chintan S. Thakkar , Kun-Yung Chang , Ting Wu
CPC classification number: H04L25/03057 , H04L7/0045 , H04L7/0058 , H04L7/0087 , H04L25/03063 , H04L2025/03369
Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.
Abstract translation: 多相部分响应接收器通过在至少两个时钟相位中选择的一个采样PrDFE输出值来支持各种输入数据速率。 该接收机包括一个校准电路，该校准电路对电路中的关键数据路径进行定时分析，然后使用该分析来选择用于锁存输出值的特定时钟相位。 这些技术允许来自部分响应接收机的每个相位的多路复用器输出直接驱动用于随后阶段的多路复用器的选择，即通过避免各个多路复用器输出中的不稳定性或不确定性的区域。
-
公开(公告)号：US20160087818A1
公开(公告)日：2016-03-24
申请号：US14865825
申请日：2015-09-25
Applicant: Rambus Inc.
Inventor： Chintan S. Thakkar , Kun-Yung Chang , Ting Wu
CPC classification number: H04L25/03057 , H04L7/0045 , H04L7/0058 , H04L7/0087 , H04L25/03063 , H04L2025/03369
Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.
-
Patent Agency Ranking
公开(公告)号：US09419827B2
公开(公告)日：2016-08-16
申请号：US14865825
申请日：2015-09-25
Applicant: Rambus Inc.
Inventor： Chintan S. Thakkar , Kun-Yung Chang , Ting Wu
CPC classification number: H04L25/03057 , H04L7/0045 , H04L7/0058 , H04L7/0087 , H04L25/03063 , H04L2025/03369
Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.
-
公开(公告)号：US20150312062A1
公开(公告)日：2015-10-29
申请号：US14687721
申请日：2015-04-15
Applicant: Rambus Inc.
Inventor： Chintan S. Thakkar , Kun-Yung Chang , Ting Wu
CPC classification number: H04L25/03057 , H04L7/0045 , H04L7/0058 , H04L7/0087 , H04L25/03063 , H04L2025/03369
Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.
Abstract translation: 多相部分响应接收器通过在至少两个时钟相位中选择的一个采样PrDFE输出值来支持各种输入数据速率。 该接收机包括一个校准电路，该校准电路对电路中的关键数据路径进行定时分析，然后使用该分析来选择用于锁存输出值的特定时钟相位。 这些技术允许来自部分响应接收机的每个相位的多路复用器输出直接驱动用于随后阶段的多路复用器的选择，即通过避免各个多路复用器输出中的不稳定性或不确定性的区域。
-
8.发明授权公开(公告)号：US10003479B2
公开(公告)日：2018-06-19
申请号：US15677421
申请日：2017-08-15
Applicant: Rambus Inc.
Inventor： Chintan S. Thakkar , Kun-Yung Chang , Ting Wu
CPC classification number: H04L25/03057 , H04L7/0045 , H04L7/0058 , H04L7/0087 , H04L25/03063 , H04L2025/03369
Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.
-
公开(公告)号：US09178726B1
公开(公告)日：2015-11-03
申请号：US14687721
申请日：2015-04-15
Applicant: Rambus Inc.
Inventor： Chintan S. Thakkar , Kun-Yung Chang , Ting Wu
CPC classification number: H04L25/03057 , H04L7/0045 , H04L7/0058 , H04L7/0087 , H04L25/03063 , H04L2025/03369
Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.
Abstract translation: 多相部分响应接收器通过在至少两个时钟相位中选择的一个采样PrDFE输出值来支持各种输入数据速率。 该接收机包括一个校准电路，该校准电路对电路中的关键数据路径进行定时分析，然后使用该分析来选择用于锁存输出值的特定时钟相位。 这些技术允许来自部分响应接收机的每个相位的多路复用器输出直接驱动用于随后阶段的多路复用器的选择，即通过避免各个多路复用器输出中的不稳定性或不确定性的区域。
-
公开(公告)号：US09042438B2
公开(公告)日：2015-05-26
申请号：US14572590
申请日：2014-12-16
Applicant: Rambus Inc.
Inventor： Chintan S. Thakkar , Kun-Yung Chang , Ting Wu
CPC classification number: H04L25/03057 , H04L7/0045 , H04L7/0058 , H04L7/0087 , H04L25/03063 , H04L2025/03369
Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.
-
-
-
-
-
-
-
-
-
Search Results
10
records
(took 0.013 seconds)
