公开(公告)号：US20230420356A1

公开(公告)日：2023-12-28

申请号：US18218280

申请日：2023-07-05

Applicant: Rambus Inc.

Inventor： Shahram NIKOUKARY ,  Jonghyun CHO ,  Nitin JUNEJA ,  Ming LI

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49816

Abstract: Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals. This decreases the length of the host C/A signals from the memory controller to the memory buffer device when the memory module is placed in a system.

公开(公告)号：US20220059154A1

公开(公告)日：2022-02-24

申请号：US17309770

申请日：2019-12-11

Applicant: Rambus Inc.

Inventor： Shahram NIKOUKARY ,  Jonghyun CHO ,  Anand JAI ,  Pradeep BATRA ,  Lei LUO

IPC: G11C11/4076 ,  G06F3/06

Abstract: A memory controller integrated circuit includes a clock signal generator circuit configured to generate a plurality of strobe signals. The memory controller integrated circuit further includes a memory interface circuit coupled to the clock signal generator circuit, the memory interface circuit configured to transmit the plurality of strobe signals to a memory module, wherein each of the plurality of strobe signals is offset with respect to an adjacent strobe signal, and transmit a plurality of data signals to the memory module, wherein a first subset of the plurality of data signals comprises a first nibble and is phase aligned with a first strobe signal of the plurality of strobe signals, and wherein a second subset of the plurality of data signals comprises a second nibble and is phase aligned with a second strobe signal of the plurality of strobe signals.

公开(公告)号：US20240395310A1

公开(公告)日：2024-11-28

申请号：US18673246

申请日：2024-05-23

Applicant: Rambus Inc.

Inventor： Shahram NIKOUKARY ,  Jonghyun CHO ,  Anand JAI ,  Pradeep BATRA ,  Lei LUO

IPC: G11C11/4076 ,  G06F3/06 ,  G11C7/22

Abstract: A memory controller integrated circuit includes a clock signal generator circuit configured to generate a plurality of strobe signals. The memory controller integrated circuit further includes a memory interface circuit coupled to the clock signal generator circuit, the memory interface circuit configured to transmit the plurality of strobe signals to a memory module, wherein each of the plurality of strobe signals is offset with respect to an adjacent strobe signal, and transmit a plurality of data signals to the memory module, wherein a first subset of the plurality of data signals comprises a first nibble and is phase aligned with a first strobe signal of the plurality of strobe signals, and wherein a second subset of the plurality of data signals comprises a second nibble and is phase aligned with a second strobe signal of the plurality of strobe signals.

公开(公告)号：US20210305142A1

公开(公告)日：2021-09-30

申请号：US17264231

申请日：2019-08-12

Applicant: Rambus Inc.

Inventor： Shahram NIKOUKARY ,  Jonghyun CHO ,  Nitin JUNEJA ,  Ming LI

IPC: H01L23/498

Abstract: Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals. This decreases the length of the host C/A signals from the memory controller to the memory buffer device when the memory module is placed in a system.