公开(公告)号：US20200212917A1

公开(公告)日：2020-07-02

申请号：US16700008

申请日：2019-12-02

Applicant: Rambus Inc.

Inventor： Jared L. ZERBE ,  Brian S. LEIBOWITZ ,  Hsuan-Jung SU ,  John Cronan EBLE, III ,  Barry William DALY ,  Lei LUO ,  Teva J. STONE ,  John WILSON ,  Jihong REN ,  Wayne D. DETTLOFF

IPC: H03L7/091 ,  H03L7/099 ,  H03L7/08 ,  H04L7/033 ,  H04L7/00 ,  H03L7/00 ,  G11C7/22 ,  G11C7/10 ,  H03K5/156

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

公开(公告)号：US20220059154A1

公开(公告)日：2022-02-24

申请号：US17309770

申请日：2019-12-11

Applicant: Rambus Inc.

Inventor： Shahram NIKOUKARY ,  Jonghyun CHO ,  Anand JAI ,  Pradeep BATRA ,  Lei LUO

IPC: G11C11/4076 ,  G06F3/06

Abstract: A memory controller integrated circuit includes a clock signal generator circuit configured to generate a plurality of strobe signals. The memory controller integrated circuit further includes a memory interface circuit coupled to the clock signal generator circuit, the memory interface circuit configured to transmit the plurality of strobe signals to a memory module, wherein each of the plurality of strobe signals is offset with respect to an adjacent strobe signal, and transmit a plurality of data signals to the memory module, wherein a first subset of the plurality of data signals comprises a first nibble and is phase aligned with a first strobe signal of the plurality of strobe signals, and wherein a second subset of the plurality of data signals comprises a second nibble and is phase aligned with a second strobe signal of the plurality of strobe signals.

公开(公告)号：US20240395310A1

公开(公告)日：2024-11-28

申请号：US18673246

申请日：2024-05-23

Applicant: Rambus Inc.

Inventor： Shahram NIKOUKARY ,  Jonghyun CHO ,  Anand JAI ,  Pradeep BATRA ,  Lei LUO

IPC: G11C11/4076 ,  G06F3/06 ,  G11C7/22

Abstract: A memory controller integrated circuit includes a clock signal generator circuit configured to generate a plurality of strobe signals. The memory controller integrated circuit further includes a memory interface circuit coupled to the clock signal generator circuit, the memory interface circuit configured to transmit the plurality of strobe signals to a memory module, wherein each of the plurality of strobe signals is offset with respect to an adjacent strobe signal, and transmit a plurality of data signals to the memory module, wherein a first subset of the plurality of data signals comprises a first nibble and is phase aligned with a first strobe signal of the plurality of strobe signals, and wherein a second subset of the plurality of data signals comprises a second nibble and is phase aligned with a second strobe signal of the plurality of strobe signals.

公开(公告)号：US20200258557A1

公开(公告)日：2020-08-13

申请号：US16793638

申请日：2020-02-18

Applicant: Rambus Inc.

Inventor： Thomas GIOVANNINI ,  Scott C. BEST ,  Lei LUO ,  Ian SHAEFFER

IPC: G11C7/22 ,  G11C29/02 ,  G11C29/50 ,  G11C29/56

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

公开(公告)号：US20190238142A1

公开(公告)日：2019-08-01

申请号：US16242475

申请日：2019-01-08

Applicant: Rambus Inc.

Inventor： Jared L. ZERBE ,  Brian S. LEIBOWITZ ,  Hsuan-Jung SU ,  John Cronan EBLE, III ,  Barry William DALY ,  Lei LUO ,  Teva J. STONE ,  John WILSON ,  Jihong REN ,  Wayne D. DETTLOFF

IPC: H03L7/091 ,  H03L7/099 ,  H03L7/08 ,  G11C7/10 ,  H03L7/00 ,  H04L7/00 ,  H03K5/156 ,  H04L7/033 ,  G11C7/22

CPC classification number: H03L7/091 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  H03K5/1565 ,  H03L7/00 ,  H03L7/0802 ,  H03L7/099 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/033

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.