公开(公告)号：US11258641B2

公开(公告)日：2022-02-22

申请号：US17181883

申请日：2021-02-22

Applicant: Rambus Inc.

Inventor： Nanyan Wang ,  Vadim Moshinsky ,  Prashant Choudhary

IPC: H04L25/03 ,  H04L27/02

Abstract: Optimized continuous time linear equalization (CTLE) circuit parameters for a received signal are found using an iterative search process. The received signal is repeatedly sampled by an analog-to-digital converter (ADC). Certain samples containing interference that cannot be cancelled by a CTLE in the sampled series are filtered out (discarded). The remaining samples are used to generate, over a selected evaluation window, a histogram of the sampled values. This histogram is used to calculate a figure of merit for the current CTLE parameter settings. The figures of merit for various CTLE parameter settings are compared to find the set of CTLE parameter settings that optimize the figure of merit and by extension, optimize the CTLE circuitry's performance at equalizing the received signal.

公开(公告)号：US11582074B2

公开(公告)日：2023-02-14

申请号：US17576501

申请日：2022-01-14

Applicant: Rambus Inc.

Inventor： Nanyan Wang ,  Vadim Moshinsky ,  Prashant Choudhary

IPC: H04L25/03 ,  H04L27/02

Abstract: Optimized continuous time linear equalization (CTLE) circuit parameters for a received signal are found using an iterative search process. The received signal is repeatedly sampled by an analog-to-digital converter (ADC). Certain samples containing interference that cannot be cancelled by a CTLE in the sampled series are filtered out (discarded). The remaining samples are used to generate, over a selected evaluation window, a histogram of the sampled values. This histogram is used to calculate a figure of merit for the current CTLE parameter settings. The figures of merit for various CTLE parameter settings are compared to find the set of CTLE parameter settings that optimize the figure of merit and by extension, optimize the CTLE circuitry's performance at equalizing the received signal.