公开(公告)号：US20210306187A1

公开(公告)日：2021-09-30

申请号：US17265294

申请日：2019-07-31

Applicant: Rambus Inc.

Inventor： Prashant Choudhary ,  Nanyang Wang

IPC: H04L25/03

Abstract: An equalizer includes a first feed-forward stage that provides a measure of low-frequency IS I and a second feed-forward stage that includes a cascade of stages each making an IS I estimate. The IS I estimate from each stage is further equalized by application of the measures of low-frequency IS I from the first feed-forward stage and fed to the next in the cascade of stages. The IS I estimate from the stages thus become progressively more accurate. The number of stages applied to a given signal can be optimized to achieve a suitably low bit-error rate. Power is saved by disabling stages which are not required to meet that goal.

公开(公告)号：US11258641B2

公开(公告)日：2022-02-22

申请号：US17181883

申请日：2021-02-22

Applicant: Rambus Inc.

Inventor： Nanyan Wang ,  Vadim Moshinsky ,  Prashant Choudhary

IPC: H04L25/03 ,  H04L27/02

Abstract: Optimized continuous time linear equalization (CTLE) circuit parameters for a received signal are found using an iterative search process. The received signal is repeatedly sampled by an analog-to-digital converter (ADC). Certain samples containing interference that cannot be cancelled by a CTLE in the sampled series are filtered out (discarded). The remaining samples are used to generate, over a selected evaluation window, a histogram of the sampled values. This histogram is used to calculate a figure of merit for the current CTLE parameter settings. The figures of merit for various CTLE parameter settings are compared to find the set of CTLE parameter settings that optimize the figure of merit and by extension, optimize the CTLE circuitry's performance at equalizing the received signal.

公开(公告)号：US11582074B2

公开(公告)日：2023-02-14

申请号：US17576501

申请日：2022-01-14

Applicant: Rambus Inc.

Inventor： Nanyan Wang ,  Vadim Moshinsky ,  Prashant Choudhary

IPC: H04L25/03 ,  H04L27/02

Abstract: Optimized continuous time linear equalization (CTLE) circuit parameters for a received signal are found using an iterative search process. The received signal is repeatedly sampled by an analog-to-digital converter (ADC). Certain samples containing interference that cannot be cancelled by a CTLE in the sampled series are filtered out (discarded). The remaining samples are used to generate, over a selected evaluation window, a histogram of the sampled values. This histogram is used to calculate a figure of merit for the current CTLE parameter settings. The figures of merit for various CTLE parameter settings are compared to find the set of CTLE parameter settings that optimize the figure of merit and by extension, optimize the CTLE circuitry's performance at equalizing the received signal.

公开(公告)号：US11502879B2

公开(公告)日：2022-11-15

申请号：US17265294

申请日：2019-07-31

Applicant: Rambus Inc.

Inventor： Prashant Choudhary ,  Nanyang Wang

IPC: H04L25/03

Abstract: An equalizer includes a first feed-forward stage that provides a measure of low-frequency IS I and a second feed-forward stage that includes a cascade of stages each making an IS I estimate. The IS I estimate from each stage is further equalized by application of the measures of low-frequency IS I from the first feed-forward stage and fed to the next in the cascade of stages. The IS I estimate from the stages thus become progressively more accurate. The number of stages applied to a given signal can be optimized to achieve a suitably low bit-error rate. Power is saved by disabling stages which are not required to meet that goal.

公开(公告)号：US20230119007A1

公开(公告)日：2023-04-20

申请号：US17978422

申请日：2022-11-01

Applicant: Rambus Inc.

Inventor： Prashant Choudhary ,  Nanyang Wang

IPC: H04L25/03

Abstract: An equalizer includes a first feed-forward stage that provides a measure of low-frequency ISI and a second feed-forward stage that includes a cascade of stages each making an ISI estimate . The ISI estimate from each stage is further equalized by application of the measures of low-frequency ISI from the first feed-forward stage and fed to the next in the cascade of stages. The ISI estimates from the stages thus become progressively more accurate. The number of stages applied to a given signal can be optimized to achieve a suitably low bit-error rate. Power is saved by disabling stages which are not required to meet that goal.