公开(公告)号：US20140140133A1

公开(公告)日：2014-05-22

申请号：US14164761

申请日：2014-01-27

Applicant: Renesas Electronics Corporation

Inventor： Hideaki YAMAKOSHI ,  Yasushi OKA ,  Daisuke OKADA

IPC: G11C16/04 ,  G11C5/06

CPC classification number: G11C16/0441 ,  G11C5/06 ,  G11C16/0433 ,  H01L27/11519 ,  H01L27/11521

Abstract: To improve performance of a semiconductor device having a nonvolatile memory. Further to improve reliability of the semiconductor device. Furthermore, to improve performance of a semiconductor device as well as improving reliability of the semiconductor device.A plurality of memory cells each configured by a memory transistor having a floating gate and a control transistor coupled in series to the memory transistor is arranged in an array in an X direction and in a Y direction on the main surface of a semiconductor substrate. Then, a bit wire that couples drain regions of the memory transistors of the memory cells arranged in the X direction is provided in the lowermost wiring layer of a multilayer wiring structure formed over the semiconductor substrate and the bit wire is arranged to cover the whole floating gate electrode.

Abstract translation: 为了提高具有非易失性存储器的半导体器件的性能。 进一步提高半导体器件的可靠性。 此外，为了提高半导体器件的性能以及提高半导体器件的可靠性。 每个由具有浮动栅极和与存储晶体管串联耦合的控制晶体管的存储晶体管构成的多个存储单元在半导体衬底的主表面上沿X方向和Y方向排列。 然后，在形成在半导体衬底上的多层布线结构的最下层布线层中设置有将在X方向排列的存储单元的存储晶体管的漏极区域连接的位线，并且位线布置成覆盖整个浮置 栅电极。