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    TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING ENHANCED ACROSS-SUBSTRATE UNIFORMITY
    1.
    发明申请
    TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING ENHANCED ACROSS-SUBSTRATE UNIFORMITY 有权
    具有嵌入式SI / GE材料的晶体管，具有增强的基板均匀性

    公开(公告)号：US20100078691A1

    公开(公告)日：2010-04-01

    申请号：US12562437

    申请日：2009-09-18

    申请人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Casey Scott

    发明人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Casey Scott

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/78

    摘要： In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behavior, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability.

    摘要翻译： 在复杂的半导体器件中，应变诱导半导体合金可以通过基于湿化学蚀刻工艺形成空腔来定位，靠近沟道区域，其可以相对于不同的晶体取向具有各向异性蚀刻行为。 在一个实施方案中，可以使用TMAH，除了各向异性蚀刻行为之外，还显示出相对于二氧化硅的高蚀刻选择性，从而使极细的蚀刻停止层可以进一步减少与沟道区的偏移 同时不会对整体过程变化造成过分的不利影响。

    TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING ENHANCED ACROSS-SUBSTRATE UNIFORMITY
    2.
    发明申请
    TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING ENHANCED ACROSS-SUBSTRATE UNIFORMITY 有权
    具有嵌入式SI / GE材料的晶体管，具有增强的基板均匀性

    公开(公告)号：US20120211810A1

    公开(公告)日：2012-08-23

    申请号：US13454177

    申请日：2012-04-24

    申请人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Casey Scott

    发明人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Casey Scott

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/78

    摘要： In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behavior, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability.

    摘要翻译： 在复杂的半导体器件中，应变诱导半导体合金可以通过基于湿化学蚀刻工艺形成空腔来定位，靠近沟道区域，其可以相对于不同的晶体取向具有各向异性蚀刻行为。 在一个实施方案中，可以使用TMAH，除了各向异性蚀刻行为之外，还显示出相对于二氧化硅的高蚀刻选择性，从而使极细的蚀刻停止层可以进一步减少与沟道区的偏移 同时不会对整体过程变化造成过分的不利影响。

    Transistor with embedded Si/Ge material having enhanced across-substrate uniformity
    3.
    发明授权
    Transistor with embedded Si/Ge material having enhanced across-substrate uniformity 有权
    具有嵌入式Si / Ge材料的晶体管具有增强的跨基板均匀性

    公开(公告)号：US08334569B2

    公开(公告)日：2012-12-18

    申请号：US13454177

    申请日：2012-04-24

    申请人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Casey Scott

    发明人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Casey Scott

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/78

    摘要： In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behavior, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability.

    摘要翻译： 在复杂的半导体器件中，应变诱导半导体合金可以通过基于湿化学蚀刻工艺形成空腔来定位，靠近沟道区域，其可以相对于不同的晶体取向具有各向异性蚀刻行为。 在一个实施方案中，可以使用TMAH，除了各向异性蚀刻行为之外，还显示出相对于二氧化硅的高蚀刻选择性，从而使极细的蚀刻停止层可以进一步减少与沟道区的偏移 同时不会对整体过程变化造成过分的不利影响。

    Transistor with embedded SI/GE material having enhanced across-substrate uniformity
    4.
    发明授权
    Transistor with embedded SI/GE material having enhanced across-substrate uniformity 有权
    具有嵌入式SI / GE材料的晶体管具有增强的跨基板均匀性

    公开(公告)号：US08183100B2

    公开(公告)日：2012-05-22

    申请号：US12562437

    申请日：2009-09-18

    申请人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Casey Scott

    发明人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Casey Scott

    IPC分类号： H01L21/84

    CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/78

    摘要： In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behavior, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability.

    摘要翻译： 在复杂的半导体器件中，应变诱导半导体合金可以通过基于湿化学蚀刻工艺形成空腔来定位，靠近沟道区域，其可以相对于不同的晶体取向具有各向异性蚀刻行为。 在一个实施方案中，可以使用TMAH，除了各向异性蚀刻行为之外，还显示出相对于二氧化硅的高蚀刻选择性，从而使极细的蚀刻停止层可以进一步减少与沟道区的偏移 同时不会对整体过程变化造成过分的不利影响。

    Multiple gate transistor having fins with a length defined by the gate electrode
    6.
    发明授权
    Multiple gate transistor having fins with a length defined by the gate electrode 有权
    多栅极晶体管具有由栅电极限定的长度的散热片

    公开(公告)号：US08183101B2

    公开(公告)日：2012-05-22

    申请号：US12620265

    申请日：2009-11-17

    申请人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Andrew Waite

    发明人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Andrew Waite

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66795 ,  H01L29/785

    摘要： The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeholder structures so as to expose the channel area of the transistor. Thereafter, corresponding fins may be patterned and a gate electrode structure may be formed. Consequently, reduced cycle times may be accomplished due to the avoidance of the epitaxial growth process.

    摘要翻译： 多栅极晶体管的漏极和源极区可以通过使用用于形成漏极和源极掺杂物分布的占位符结构而形成，而不需要外延生长工艺，随后掩蔽漏极和源极区域并去除占位符结构以露出​​沟道 晶体管的面积。 此后，可以对相应的翅片进行构图，并且可以形成栅电极结构。 因此，由于避免了外延生长过程，可以实现缩短的循环时间。

    GRADED WELL IMPLANTATION FOR ASYMMETRIC TRANSISTORS HAVING REDUCED GATE ELECTRODE PITCHES
    7.
    发明申请
    GRADED WELL IMPLANTATION FOR ASYMMETRIC TRANSISTORS HAVING REDUCED GATE ELECTRODE PITCHES 有权
    具有减少栅极电极板的不对称晶体管的分级井植入

    公开(公告)号：US20100193866A1

    公开(公告)日：2010-08-05

    申请号：US12692886

    申请日：2010-01-25

    申请人： G Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Vassilios Papageorgiou

    发明人： G Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Vassilios Papageorgiou

    IPC分类号： H01L27/088 ,  H01L21/77

    CPC分类号： H01L21/266 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833

    摘要： In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of an asymmetric well implantation while avoiding a tilted implantation process. For this purpose, a graded implantation mask may be formed, such as a graded resist mask, which may have a higher ion blocking capability at the drain side compared to the source side of the asymmetric transistor. For instance, the asymmetric configuration may be obtained on the basis of a non-tilted implantation process with a high degree of performance gain and may be accomplished irrespective of the technology standard under consideration.

    摘要翻译： 在复杂的半导体器件中，可以在不对称阱注入的基础上获得不对称晶体管配置，同时避免倾斜的注入工艺。 为此，可以形成渐变注入掩模，例如渐变抗蚀剂掩模，其在不对称晶体管的源极侧可能在漏极侧具有更高的离子阻挡能力。 例如，可以在具有高度性能增益的非倾斜注入工艺的基础上获得不对称构造，并且可以不考虑所考虑的技术标准而实现。

    MULTIPLE GATE TRANSISTOR HAVING FINS WITH A LENGTH DEFINED BY THE GATE ELECTRODE
    8.
    发明申请
    MULTIPLE GATE TRANSISTOR HAVING FINS WITH A LENGTH DEFINED BY THE GATE ELECTRODE 有权
    具有由门电极定义的长度的多个栅极晶体管

    公开(公告)号：US20100133615A1

    公开(公告)日：2010-06-03

    申请号：US12620265

    申请日：2009-11-17

    申请人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Andrew Waite

    发明人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Andrew Waite

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66795 ,  H01L29/785

    摘要： The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeholder structures so as to expose the channel area of the transistor. Thereafter, corresponding fins may be patterned and a gate electrode structure may be formed. Consequently, reduced cycle times may be accomplished due to the avoidance of the epitaxial growth process.

    摘要翻译： 多栅极晶体管的漏极和源极区可以通过使用用于形成漏极和源极掺杂物分布的占位符结构而形成，而不需要外延生长工艺，随后掩蔽漏极和源极区域并去除占位符结构以露出​​沟道 晶体管的面积。 此后，可以对相应的翅片进行构图，并且可以形成栅电极结构。 因此，由于避免了外延生长过程，可以实现缩短的循环时间。