公开(公告)号：US20240339446A1

公开(公告)日：2024-10-10

申请号：US18297182

申请日：2023-04-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Ying Lai ,  Po-Chih Su ,  Ruey-Hsin Liu

IPC分类号： H01L27/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0255 ,  H01L21/823493 ,  H01L27/0296 ,  H01L29/0607 ,  H01L29/66689 ,  H01L29/7818 ,  H03K17/08104

摘要： Damage to an LDMOS transistor from voltage overshoot in a power switching circuit operating at high switching speeds is prevented by embedding a diode under a drain region of the LDMOS transistor. The embedded diode is doped more heavily than a drift region of the LDMOS transistor and lowers a breakdown voltage of the LDMOS transistor.

公开(公告)号：US12027573B2

公开(公告)日：2024-07-02

申请号：US17579543

申请日：2022-01-19

申请人： Vanguard International Semiconductor Corporation

发明人： Yu-Jui Chang ,  Chien-Hsien Song ,  Kai-Chuan Kan

IPC分类号： H01L49/02 ,  H01L21/8234 ,  H01L27/06

CPC分类号： H01L28/20 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0629 ,  H01L28/24

摘要： A semiconductor device includes a substrate, a first well region, a second well region, an isolation region, a first resistor segment and a second resistor segment. The substrate includes a region having a first conductivity type. The first and the second well regions are disposed in the region of the substrate. The isolation region is disposed on the first and the second well regions. The first and the second resistor segments are electrically connected to each other and disposed on the isolation region. Moreover, the first and the second well regions are disposed directly under the first and the second resistor segments, respectively. The first and the second well regions do not overlap with each other in a vertical projection direction and have a second conductivity type that is opposite to the first conductivity type.

公开(公告)号：US20240194782A1

公开(公告)日：2024-06-13

申请号：US18581728

申请日：2024-02-20

申请人： Silergy Semiconductor Technology (Hangzhou) LTD

发明人： Meng Wang ,  Yicheng Du ,  Hui Yu

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/7816 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/66681

摘要： A semiconductor device having an LDMOS transistor can include: a first deep well region having a first doping type; a drift region located in the first deep well region and having a second doping type; and a drain region located in the drift region and having the second doping type, where the second doping type is opposite to the first doping type, and where a doping concentration peak of the first deep well region is located below the drift region to optimize the breakdown voltage and the on-resistance of the LDMOS transistor.

公开(公告)号：US11942540B2

公开(公告)日：2024-03-26

申请号：US16416420

申请日：2019-05-20

申请人： Silergy Semiconductor Technology (Hangzhou) LTD

发明人： Meng Wang ,  Yicheng Du ,  Hui Yu

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/7816 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/66681

摘要： A semiconductor device having an LDMOS transistor can include: a first deep well region having a first doping type; a drift region located in the first deep well region and having a second doping type; and a drain region located in the drift region and having the second doping type, where the second doping type is opposite to the first doping type, and where a doping concentration peak of the first deep well region is located below the drift region to optimize the breakdown voltage and the on-resistance of the LDMOS transistor.

公开(公告)号：US20180366413A1

公开(公告)日：2018-12-20

申请号：US15687362

申请日：2017-08-25

申请人： QUALCOMM Incorporated

发明人： Ye LU ,  Bin YANG ,  Junjing BAO

IPC分类号： H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02

CPC分类号： H01L23/53295 ,  C01B32/182 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/02321 ,  H01L21/02362 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76822 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/823493 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L29/78 ,  H01L29/7851

摘要： An integrated circuit may include multiple back-end-of-line (BEOL) interconnect layers. The BEOL interconnect layers may include conductive lines and conductive vias. The integrated circuit may further include an interlayer dielectric (ILD) between the BEOL interconnect layers. The ILD may include the conductive lines and the conductive vias. At least a portion of the ILD may include a low-K insulating graphene alloy.

公开(公告)号：US20180331226A1

公开(公告)日：2018-11-15

申请号：US16033288

申请日：2018-07-12

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： John B. CAMPI, JR. ,  Robert J. GAUTHIER, JR. ,  Rahul MISHRA ,  Souvick MITRA ,  Mujahid MUHAMMAD

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/266 ,  H01L21/265 ,  H01G4/33 ,  H01G4/30 ,  H01G4/228 ,  H01G4/14 ,  H01G4/005 ,  B32B27/36 ,  B32B27/34 ,  B32B27/32 ,  B32B27/30 ,  B32B27/28 ,  B32B27/08 ,  B32B27/00 ,  B32B7/02 ,  B32B3/08 ,  B29C47/56 ,  B29C47/06 ,  B29C37/00 ,  B29K23/00 ,  B29L31/34 ,  B29L9/00 ,  B29K507/04 ,  B29K105/16

CPC分类号： H01L27/0886 ,  B29C37/0025 ,  B29C47/065 ,  B29C47/56 ,  B29K2023/12 ,  B29K2105/16 ,  B29K2507/04 ,  B29K2995/0005 ,  B29K2995/0007 ,  B29L2009/003 ,  B29L2009/005 ,  B29L2031/34 ,  B32B3/08 ,  B32B7/02 ,  B32B27/00 ,  B32B27/08 ,  B32B27/28 ,  B32B27/306 ,  B32B27/308 ,  B32B27/32 ,  B32B27/34 ,  B32B27/36 ,  B32B2262/106 ,  B32B2264/105 ,  B32B2264/12 ,  B32B2270/00 ,  B32B2274/00 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2307/206 ,  B32B2307/518 ,  B32B2307/732 ,  B32B2457/16 ,  H01G4/005 ,  H01G4/14 ,  H01G4/228 ,  H01G4/30 ,  H01G4/33 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66681 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/66795 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7816 ,  H01L29/7825 ,  H01L29/7851 ,  H01L29/7856 ,  H01L2029/7858

摘要： A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

公开(公告)号：US20180315818A1

公开(公告)日：2018-11-01

申请号：US15499020

申请日：2017-04-27

申请人： Texas Instruments Incorporated

发明人： Binghua Hu ,  Azghar H Khazi-Syed ,  Shariq Arshad

IPC分类号： H01L29/10 ,  H01L21/265 ,  H01L21/266 ,  H01L21/225 ,  H01L21/02 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/06 ,  H01L27/088

CPC分类号： H01L29/1083 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/2253 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0653

摘要： A microelectronic device having an n-type buried layer (NBL) is formed by forming a thin screen layer on the top surface of the substrate. Antimony is implanted through the screen layer exposed by an implant mask into the substrate; the implant mask blocks antimony from the substrate outside the NBL area. The implant mask is removed, leaving the screen layer, which has the same thickness over the NBL area and the area outside the NBL, on the surface. Silicon dioxide is formed during an anneal/drive process, both in the NBL area and outside the NBL area. Slightly more silicon dioxide is formed in the NBL area, consuming more silicon there and so forming a shallow silicon recess. An epitaxial layer is grown on the top surface of the substrate. A structure for the microelectronic device is also disclosed.

公开(公告)号：US20180197857A1

公开(公告)日：2018-07-12

申请号：US15916756

申请日：2018-03-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Yao Wen ,  Sai-Hooi Yeong ,  Sheng-chen Wang

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L27/02

CPC分类号： H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0207 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/78615

摘要： A semiconductor device includes multiple first fins oriented lengthwise along a first direction and multiple first gate structures oriented lengthwise along a second direction generally perpendicular to the first direction. Each of the first fins includes an end that is narrower than a main body of the respective first fin. The first gate structures are disposed over channel regions of the main body of the first fins to form multiple first FinFETs. The end of the first fins and the channel regions of the first fins sandwich some of source/drain regions of the first fins. The semiconductor device further includes a first contact disposed over and in electrical contact with the ends of the first fins.

公开(公告)号：US20180190754A1

公开(公告)日：2018-07-05

申请号：US15593479

申请日：2017-05-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yu-Chiun LIN ,  Po-Nien CHEN ,  Chen Hua TSAI ,  Chih-Yung LIN

IPC分类号： H01L49/02 ,  H01L29/10 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/3205 ,  H01L27/06

CPC分类号： H01L28/24 ,  H01L21/32051 ,  H01L21/823431 ,  H01L21/823493 ,  H01L21/823821 ,  H01L23/5228 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0924 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

公开(公告)号：US09997539B2

公开(公告)日：2018-06-12

申请号：US15251222

申请日：2016-08-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Horacio Mendez

发明人： Terence B. Hook ,  Horacio Mendez

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L27/092 ,  H01L21/326 ,  H01L21/8234 ,  H01L29/36 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/265

CPC分类号： H01L27/1203 ,  H01L21/2652 ,  H01L21/326 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0925 ,  H01L29/0649 ,  H01L29/36

摘要： A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage; and a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage. The second voltage is different than the first voltage.