公开(公告)号：US20230005412A1

公开(公告)日：2023-01-05

申请号：US17931311

申请日：2022-09-12

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： CHOLHO KIM ,  GUNWOO YANG ,  HYUNYOUNG CHOI ,  JIHOON YANG ,  YONGWOO LEE

IPC: G09G3/20 ,  G11C19/28 ,  G09G3/36 ,  G09G3/3266

Abstract: A gate driver according to an exemplary embodiment of the present inventive concept includes a pull-up-pull-down circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration and configured to pull down the gate signal to a low level of the first clock signal in a second duration, and a pull-down boosting circuit configured to output a first off voltage to the pull-up-pull-down part in the second duration in response to a second clock signal.

公开(公告)号：US20170249893A1

公开(公告)日：2017-08-31

申请号：US15412691

申请日：2017-01-23

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： CHOLHO KIM ,  GUNWOO YANG ,  HYUNYOUNG CHOI ,  JIHOON YANG ,  YONGWOO LEE

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0223 ,  G11C19/28

Abstract: A gate driver according to an exemplary embodiment of the present inventive concept includes a pull-up-pull-down circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration and configured to pull down the gate signal to a low level of the first clock signal in a second duration, and a pull-down boosting circuit configured to output a first off voltage to the pull-up-pull-down part in the second duration in response to a second clock signal.

公开(公告)号：US20250078756A1

公开(公告)日：2025-03-06

申请号：US18819628

申请日：2024-08-29

Applicant: Samsung Display Co., Ltd.

Inventor： IN SOO WANG ,  SANG YONG NO ,  KEUK-JIN JEONG ,  YONGWOO LEE

IPC: G09G3/3233

Abstract: A pixel includes a driving switching element including a control electrode connected to a first node, a first electrode connected to a second node and a second electrode connected to a third node, a writing switching element including a control electrode receiving a writing gate signal, a first electrode receiving a data voltage and a second electrode connected to the second node, a compensation switching element including a control electrode receiving a compensation gate signal, a first electrode connected to the first node and a second electrode connected to the third node, a storage capacitor including a first electrode receiving a first power voltage and a second electrode connected to the first node, the light emitting element emitting a light based on a driving current flowing through the driving switching element. The writing gate signal is n-th stage gate signal. The compensation gate signal is (n+k)-th stage gate signal.

公开(公告)号：US20250014509A1

公开(公告)日：2025-01-09

申请号：US18754149

申请日：2024-06-26

Applicant: Samsung Display Co., Ltd.

Inventor： JIYOUNG LEE ,  SOHAE KIM ,  Jisong Chae ,  SANG-GU LEE ,  YONGWOO LEE ,  HYUNG UK CHO ,  HYUNYOUNG CHOI

IPC: G09G3/32

Abstract: A pixel circuit includes a first transistor including a control electrode connected to a second node, a first electrode receiving a first power supply voltage, and a second electrode connected to a third node, a second transistor including a control electrode receiving a write signal, a first electrode connected to a data line, and a second electrode connected to a first node, a third transistor including a control electrode receiving a compensation signal, a first electrode connected to the second node, and a second electrode connected to the third node, a fourth transistor including a control electrode receiving an initialization signal, a first electrode receiving an initialization voltage, and a second electrode connected to a fourth node, a fifth transistor including a control electrode connected to the first node, a first electrode connected to the third node, and a second electrode connected to the fourth node, and a light emit element including a first electrode connected to the fourth node.

公开(公告)号：US20170263177A1

公开(公告)日：2017-09-14

申请号：US15447748

申请日：2017-03-02

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： CHOLHO KIM ,  GUNWOO YANG ,  JIHOON YANG ,  YONGWOO LEE ,  HYUNYOUNG CHOI

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G11C19/28

Abstract: An N-th stage of a gate driver includes a first control circuit, a gate signal generating circuit, a carry signal generating circuit, a second control circuit, a third control circuit, and a holding circuit. The first control circuit controls a first signal in response to a first input signal. The gate signal generating circuit generates a gate signal in response to a clock signal and the first signal. The carry signal generating circuit generates a carry signal in response to the clock signal and the first signal. The second control circuit controls the first signal in response to a second input signal. The third control circuit generates a hold control signal in response to a third input signal having a frequency lower than the clock signal's. The holding circuit maintains levels of the first signal, the gate signal, and the carry signal in response to the hold control signal.